SNOSDF6 October   2023 LM74930-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Charge Pump
      2. 7.3.2  Dual Gate Control (DGATE, HGATE)
        1. 7.3.2.1 Load Disconnect Switch Control (HGATE, OUT)
        2. 7.3.2.2 Reverse Battery Protection (A, C, DGATE)
      3. 7.3.3  Overcurrent Protection (CS+, CS-, ILIM, IMON, TMR)
      4. 7.3.4  Overcurrent Protection with Circuit Breaker (ILIM, TMR)
      5. 7.3.5  Overcurrent Protection With Latch-Off
      6. 7.3.6  Short-Circuit Protection (ISCP)
        1. 7.3.6.1 Device Wake-Up With Output Short-Circuit Condition
      7. 7.3.7  Analog Current Monitor Output (IMON)
      8. 7.3.8  Overvoltage and Undervoltage Protection (OV, UVLO, OVCLAMP)
      9. 7.3.9  Disabling Reverse Current Blocking Functionality (MODE)
      10. 7.3.10 Device Functional Modes
        1. 7.3.10.1 Low Quiescent Current Shutdown Mode (EN)
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: 200-V Unsuppressed Load Dump Protection Application
      1. 8.2.1 Design Requirements for 200-V Unsuppressed Load Dump Protection
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  VS Capacitance, Resistor R1 and Zener Clamp (DZ)
        2. 8.2.2.2  Charge Pump Capacitance VCAP
        3. 8.2.2.3  Input and Output Capacitance
        4. 8.2.2.4  Overvoltage and Undervoltage Protection Component Selection
        5. 8.2.2.5  Selection of Scaling Resistor (RSET) and Short-Circuit Protection Setting Resistor (RSCP)
        6. 8.2.2.6  Overcurrent Limit (ILIM), Circuit Breaker Timer (TMR), and Current Monitoring Output (IMON) Selection
        7. 8.2.2.7  Selection of Current Sense Resistor, RSNS
        8. 8.2.2.8  Hold-Up Capacitance
        9. 8.2.2.9  MOSFET Q1 Selection
        10. 8.2.2.10 MOSFET Q2 Selection
        11. 8.2.2.11 Input TVS Selection
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Transient Protection
      2. 8.4.2 TVS Selection for 12-V Battery Systems
      3. 8.4.3 TVS Selection for 24-V Battery Systems
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 Overcurrent Protection with Circuit Breaker (ILIM, TMR)

LM74930-Q1 provides programmable overcurrent threshold setting by means of resistor (RLIM) connected from ILIM pin to GND.

Equation 3. RILIM=12×RSETILIM×RSENSE

where

  • RSET is the resistor connected across CS+ and VS
  • RSNS is the current sense resistor
  • ILIM is the overcurrent level

The CTMR programs the circuit breaker and auto-retry time. After the voltage across CS+ and CS– exceeds the set point, the CTMR starts charging with 85-µA pull up current. After the CTMR charges to VTMR_FLT, FLT asserts low providing warning on impending FET turn OFF. After CTMR charges to VTMR_OC, HGATE is pulled to OUT turning off the load disconnect FET. After this event, the auto-retry behavior starts. The CTMR capacitor starts discharging with 2.7-µA pull down current. After the voltage reaches VTMR_Low level, the capacitor starts charging with 2.7-µA pull up. After 32 charging/discharging cycles of CTMR, the FET turns ON and FLT de-asserts after de-assertion delay.

Equation 4. TOC=1.2×CTMR82.3 μA

where

  • TOC is the delay to turn OFF the FET
  • CTMR is the capacitance across TMR to GND

The auto-retry time can be computed as

Equation 5. TRETRY=22.7×106×CTMR

If the overcurrent pulse duration is below TOC then the FET remains ON and CTMR gets discharged using internal pull down switch.

When not used, ILIM is connected to ground while TMR can be left floating.

GUID-20231030-SS0I-SNWT-G0NX-87DJ9SNM087B-low.svgFigure 7-3 LM74930-Q1 Auto Retry TIMER Functionality
GUID-20210816-SS0I-MGTH-T5NT-BDTRW04QLPMX-low.svgFigure 7-4 Overcurrent Protection With Auto Retry Timing Diagram

If the overcurrent pulse duration is below TOC then the FET remains ON and CTMR gets discharged using internal pull down switch.