SBOSA56C March   2022  – October 2023 LMH34400

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Electrical Characteristics: Logic Threshold and Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Clamping and Input Protection
      2. 6.3.2 ESD Protection
      3. 6.3.3 Single-Ended Output Stage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Ambient Light Cancellation Mode
      2. 6.4.2 Power-Down Mode (Multiplexer Mode)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 LMH34400 Test Circuit
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 LMH34400 Signal Chain With Comparator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRL|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics: Logic Threshold and Switching Characteristics

at VDD = 3.3 V, CPD (1) = 1 pF, EN = 0 V, IDC_EN = 3.3 V, RL = 100 Ω (Output is AC-coupled for AC performance parameters; for DC performance parameters load is referenced to 1V), and TA = 25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC THRESHOLD PERFORMANCE
EN control threshold voltage Amplifier disabled above this voltage 1.6 2 V
Amplifier enabled below this voltage 0.8 1.2 V
IDC_EN control threshold voltage Ambient light cancellation loop disabled above this voltage 1.6 2 V
Ambient light cancellation loop enabled below this voltage 0.8 1.2 V
EN CONTROL TRANSIENT PERFORMANCE
Enable transition-time (1% settling) Ambient loop disabled, fIN = 25 MHz, VOUT = 1 VPP, IDC = 0 µA 200 ns
Disable transition-time (1% settling) Ambient loop disabled, fIN = 25 MHz, VOUT = 1 VPP, IDC = 0 µA 3.5 ns
Enable transition-time (1% settling) Ambient loop enabled, fIN = 25 MHz, VOUT = 1 VPP, IDC = 100 µA 10 µs
Disable transition-time (1% settling) Ambient loop enabled, fIN = 25 MHz, VOUT = 1 VPP, IDC = 100 µA 3.5 ns
(1) Input capacitance of photodiode.