SNOSA03H November   2002  – May 2016 LMH6702

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Harmonic Distortion
    3. 7.3 Device Functional Modes
      1. 7.3.1 2-Tone 3rd Order Intermodulation
      2. 7.3.2 DC Accuracy and Noise
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Feedback Resistor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
VS ±6.75 V
IOUT See(3)
Common mode input voltage V− to V+ V
Maximum junction temperature 150 °C
Storage temperature −65 150 °C
Soldering information Infrared or convection (20 s) 235 °C
Wave soldering (10 s) 260 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The maximum output current (IOUT) is determined by device power dissipation limitations.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Machine Model (MM), per JEDEC specification JESD22-C101, all pins(2) ±200
(1) Human body model: 1.5 kΩ in series with 100 pF. JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 2000-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) Machine model: 0 Ω in series with 200 pF. JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 200-V MM is possible with the necessary precautions. Pins listed as ±200 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Operating temperature −40 85 °C
Nominal supply voltage ±4 ±6 V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical Characteristics tables.

6.4 Thermal Information

THERMAL METRIC(1) LMH6702 UNIT
DBV (SOT-23) D (SOIC)
5 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 182 133 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 139 79 °C/W
RθJB Junction-to-board thermal resistance 40 73 °C/W
ψJT Junction-to-top characterization parameter 28 28 °C/W
ψJB Junction-to-board characterization parameter 40 73 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

at AV = 2, VS = ±5 V, RL = 100 Ω, RF = 237 Ω (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN(3) TYP(4) MAX(3) UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBWSM -3-dB Bandwidth VOUT = 0.5 VPP 1700 MHz
SSBWLG VOUT = 2 VPP 720
LSBWLG VOUT = 4 VPP 480
SSBWHG VOUT = 2 VPP, AV = +10 140
GF0.1dB 0.1-dB gain flatness VOUT = 2 VPP 120 MHz
LPD Linear phase deviation DC to 100 MHz 0.09 deg
DG Differential gain RL =150 Ω, 3.58 MHz 0.024%
RL =150 Ω, 4.43 MHz 0.021%
DP Differential phase RL = 150 Ω, 3.58 MHz 0.004 deg
RL = 150 Ω, 4.43 MHz 0.007
TIME DOMAIN RESPONSE
tR Rise time 2-V Step, TRS 0.87 ns
2-V Step, TRL 0.77
tF Fall time 6-V Step, TRS 1.70 ns
6-V Step, TRL 1.70
OS Overshoot 2-V Step 0%
SR Slew rate 6 VPP, 40% to 60%(2) 3100 V/µs
Ts Settling time to 0.1% 2-V Step 13.4 ns
DISTORTION AND NOISE RESPONSE
HD2L 2nd Harmonic distortion 2 VPP, 5 MHz(7) (SOT-23) −100 dBc
2 VPP, 5 MHz(7) (SOIC) −87
HD2 2VPP, 20 MHz(7) (SOT-23) −79 dBc
2VPP, 20 MHz(7) (SOIC) −72
HD2H 2VPP, 60 MHz(7) (SOT-23) −63 dBc
2VPP, 60 MHz(7) (SOIC) −64
HD3L 3rd Harmonic distortion 2VPP, 5 MHz(7) (SOT-23) −96 dBc
2VPP, 5 MHz(7) (SOIC) −98
HD3 2VPP, 20 MHz(7) (SOT-23) −88 dBc
2VPP, 20 MHz(7) (SOIC) −82
HD3H 2VPP, 60 MHz(7) (SOT-23) −70 dBc
2VPP, 60 MHz(7) (SOIC) −65
OIM3 IMD 75 MHz, PO = 10dBm/ tone −67 dBc
VN Input referred voltage noise >1 MHz 1.83 nV/√Hz
IN Input referred inverting noise current >1 MHz 18.5 pA/√Hz
INN Input referred non-inverting noise current >1 MHz 3.0 pA/√Hz
SNF Total input noise floor >1 MHz −158 dBm1Hz
INV Total integrated input noise 1 MHz to 150 MHz 35 µV
STATIC, DC PERFORMANCE
VIO Input offset voltage ±1.0 ±4.5 mV
-40 ≤ TJ ≤ 85 ±6.0
DVIO Input offset voltage average drift See(6) −13 µV/°C
IBN Input bias current Non-Inverting(5) −6 –15 µA
-40 ≤ TJ ≤ 85 –21
DIBN Input bias current average drift Non-Inverting(6) +40 nA/°C
IBI Input bias current Inverting(5) −8 ±30 µA
-40 ≤ TJ ≤ 85 ±34
DIBI Input bias current average drift Inverting(6) −10 nA/°C
PSRR Power supply rejection ratio DC 47 52 dB
-40 ≤ TJ ≤ 85 45
CMRR Common mode rejection ration DC 45 48 dB
-40 ≤ TJ ≤ 85 44
ICC Supply current RL = ∞ 11.0 12.5 16.1 mA
-40 ≤ TJ ≤ 85 10.0 17.5
MISCELLANEOUS PERFORMANCE
RIN Input resistance Non-Inverting 1.4 MΩ
CIN Input capacitance Non-Inverting 1.6 pF
ROUT Output resistance Closed Loop 30 mΩ
VOL Output voltage range RL = 100 Ω ±3.3 ±3.5 V
-40 ≤ TJ ≤ 85 ±3.2
CMIR Input voltage range Common Mode ±1.9 ±2.2 V
IO Output current 50 80 mA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Min/Max ratings are based on production testing unless otherwise specified.
(2) Slew Rate is the average of the rising and falling edges.
(3) All limits are ensured by testing or statistical analysis.
(4) Typical numbers are the most likely parametric norm.
(5) Negative input current implies current flowing out of the device.
(6) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(7) Harmonic distortion is strongly influenced by package type (SOT-23 or SOIC). See Application Note section under Harmonic Distortion for more information.

6.6 Typical Characteristics

TA = 25°C, VS = ±5 V, RL = 100 Ω, Rf = 237 Ω (unless otherwise noted)
LMH6702 20039001.gif
V0 = 2 Vpp RL = 100 Ω RF = 237 Ω
Figure 1. Non-Inverting Frequency Response
LMH6702 20039030.gif
VOUT = 0.5 VPP AV = 2 RF = 232 Ω
Figure 3. Small Signal Bandwidth
LMH6702 20039017.gif
AV = 4 VO = 2 VPP RF = 237 Ω
Figure 5. Frequency Response for Various RLs, AV = 4
LMH6702 20039006.gif
AV = 2 VOUT = 6 VPP RL = 100 Ω
Figure 7. Step Response, 6 VPP
LMH6702 20039007.gif
2 VPP AV = 2 RF = 237 Ω
Figure 9. Harmonic Distortion vs Load and Frequency
(SOIC Package)
LMH6702 20039013.gif
AV = -1 RL = 1 kΩ
Figure 11. RS and Settling Time vs CL
LMH6702 20039009.gif
AV = 2 RF = 237 Ω RL = 100 Ω
Figure 13. HD3 vs Output Power (Across 100 Ω)
(SOIC Package)
LMH6702 20039015.gif
Figure 15. Inverting Input Bias
for 3 Representative Units
LMH6702 20039012.gif
Figure 17. Noise
LMH6702 20039011.gif
VS = ±5 V RL = 100 Ω
Figure 19. Transimpedance
LMH6702 20039003.gif
RF = 237 Ω RL = 150 Ω
Figure 21. DG/DP (PAL)
LMH6702 20039002.gif
VOUT = 2 VPP RF = 237 Ω RL = 100 Ω
Figure 2. Inverting Frequency Response
LMH6702 20039018.gif
AV = 2 VO = 2 VPP RF = 237 Ω
Figure 4. Frequency Response for Various RLs, AV = 2
LMH6702 20039005.gif
VO = 2 VPP RL = 100 Ω
Figure 6. Step Response, 2 VPP
LMH6702 20039020.gif
RL = 100 Ω
Figure 8. Percent Settling vs Time
LMH6702 20039021.gif
AV = 2 RL = 100 Ω RF = 237 Ω
Figure 10. 2 Tone 3rd Order Spurious Level
(SOIC Package)
LMH6702 20039008.gif
AV = 2 RF = 237 Ω RL = 100 Ω
Figure 12. HD2 vs Output Power (Across 100 Ω)
(SOIC Package)
LMH6702 20039014.gif
Figure 14. Input Offset for 3 Representative Units
LMH6702 20039016.gif
Figure 16. Non-Inverting Input Bias for 3 Representative Units
LMH6702 20039019.gif
VS = ±5 V RL = 100 Ω
Figure 18. CMRR, PSRR, ROUT
LMH6702 20039004.gif
RF = 237 Ω RL = 150 Ω
Figure 20. DG/DP (NTSC)