SNAS597 Data sheet

SNAS597C July 2012 – January 2016 LMK04816

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

NKD|64
- MPQS032C

Thermal pad, mechanical data (Package|Pins)

NKD|64
- QFND765

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾⁽²⁾⁽³⁾.

		MIN	MAX	UNIT
V_CC	Supply voltage ⁽⁴⁾	–0.3	3.6	V
V_IN	Input voltage	–0.3	(V_CC + 0.3)	V
T_L	Lead temperature (solder 4 seconds)		260	°C
T_J	Junction temperature		150	°C
I_IN	Differential input current (CLKinX/X, OSCin/OSCin, FBCLKin/FBCLKin, Fin/Fin)		±5	mA
MSL	Moisture sensitivity level		3
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) This device is a high performance RF integrated circuit with an ESD rating up to 2-kV Human Body Model, up to 150-V Machine Model, and up to 750-V Charged Device Model and is ESD sensitive. Handling and assembly of this device must only be done at ESD-free workstations.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(4) Never to exceed 3.6 V.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±750
		Machine model (MM)	±150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary recautions. Pins listed as ±750 V may actually have higher performance. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
T_J	Junction temperature				125	°C
T_A	Ambient temperature	V_CC = 3.3 V	–40	25	85	°C
V_CC	Supply voltage		3.15	3.3	3.45	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMK04816	UNIT
		NKD (WQFN)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance ⁽²⁾	24.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance ⁽³⁾	6.1	°C/W
R_θJB	Junction-to-board thermal resistance ⁽⁴⁾	3.5	°C/W
ψ_JT	Junction-to-top characterization parameter ⁽⁵⁾	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter ⁽⁶⁾	3.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance ⁽⁷⁾	0.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, Ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, Ψ_JB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.5 Electrical Characteristics

3.15 V ≤ V_CC ≤ 3.45 V, –40°C ≤ T_A ≤ 85°C. Typical values represent most likely parametric norms at V_CC = 3.3 V, T_A = 25°C, at the Recommended Operating Conditions at the time of product characterization and are not ensured.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
I_{CC_PD}	Power-down supply current				1	3	mA
I_{CC_CLKS}	Supply current with all clocks enabled ⁽¹⁾	All clock delays disabled, CLKoutX_Y_DIV = 1045, CLKoutX_TYPE = 1 (LVDS), PLL1 and PLL2 locked.			505	590	mA
*CLKin0/0, CLKin1/1, AND CLKin2/2 INPUT CLOCK SPECIFICATIONS**
f_CLKin	Clock input frequency ⁽²⁾			0.001		500	MHz
SLEW_CLKin	Clock input slew rate ⁽³⁾⁽⁴⁾	20% to 80%		0.15	0.5		V/ns
V_IDCLKin	Clock input Differential input voltage ⁽⁵⁾ Figure 5	AC-coupled CLKinX_BUF_TYPE = 0 (bipolar)		0.25		1.55	\|V\|
V_SSCLKin		AC-coupled CLKinX_BUF_TYPE = 0 (bipolar)		0.5		3.1	Vpp
V_IDCLKin		AC-coupled CLKinX_BUF_TYPE = 1 (MOS)		0.25		1.55	\|V\|
V_SSCLKin		AC-coupled CLKinX_BUF_TYPE = 1 (MOS)		0.5		3.1	Vpp
V_CLKin	Clock input Single-ended input voltage ⁽³⁾	AC-coupled to CLKinX; CLKinX* AC-coupled to ground CLKinX_BUF_TYPE = 0 (bipolar)		0.25		2.4	Vpp
V_CLKin	Clock input Single-ended input voltage ⁽³⁾	AC-coupled to CLKinX; CLKinX* AC-coupled to ground CLKinX_BUF_TYPE = 1 (MOS)		0.25		2.4	Vpp
V_{CLKin0-offset}	DC offset voltage between CLKin0/CLKin0* CLKin0* – CLKin0	Each pin AC-coupled CLKin0_BUF_TYPE = 0 (Bipolar)			20		mV
V_{CLKin1-offset}	DC offset voltage between CLKin1/CLKin1* CLKin1* – CLKin1				0		mV
V_{CLKin2-offset}	DC offset voltage between CLKin2/CLKin2* CLKin2* – CLKin2				20		mV
V_{CLKinX-offset}	DC offset voltage between CLKinX/CLKinX* CLKinX* – CLKinX	Each pin AC-coupled CLKinX_BUF_TYPE = 1 (MOS)			55		mV
V_CLKin- V_IH	High input voltage	DC-coupled to CLKinX; CLKinX* AC-coupled to ground CLKinX_BUF_TYPE = 1 (MOS)		2.0		V_CC	V
V_CLKin- V_IL	Low input voltage			0		0.4	V
*FBCLKin/FBCLKin AND Fin/Fin* INPUT SPECIFICATIONS**
f_FBCLKin	Clock input frequency ⁽³⁾	AC-coupled (CLKinX_BUF_TYPE = 0) MODE = 2 or 8; FEEDBACK_MUX = 6		0.001		1000	MHz
f_Fin	Clock input frequency ⁽³⁾	AC-coupled (CLKinX_BUF_TYPE = 0) MODE = 3 or 11		0.001		3100	MHz
V_FBCLKin/Fin	Single-ended clock input voltage ⁽³⁾	AC-coupled; (CLKinX_BUF_TYPE = 0)		0.25		2	Vpp
SLEW_FBCLKin/Fin	Slew rate on CLKin ⁽³⁾	AC-coupled; 20% to 80%; (CLKinX_BUF_TYPE = 0)		0.15	0.5		V/ns
PLL1 SPECIFICATIONS
f_PD1	PLL1 phase detector frequency					40	MHz
I_CPout1SOURCE	PLL1 charge Pump source current ⁽⁶⁾	V_CPout1 = V_CC / 2, PLL1_CP_GAIN = 0			100		µA
		V_CPout1 = V_CC / 2, PLL1_CP_GAIN = 1			200
		V_CPout1 = V_CC / 2, PLL1_CP_GAIN = 2			400
		V_CPout1 = V_CC / 2, PLL1_CP_GAIN = 3			1600
I_CPout1SINK	PLL1 charge Pump sink current ⁽⁶⁾	V_CPout1 = V_CC / 2, PLL1_CP_GAIN = 0			–100		µA
		V_CPout1 = V_CC / 2, PLL1_CP_GAIN = 1			–200
		V_CPout1 = V_CC / 2, PLL1_CP_GAIN = 2			–400
		V_CPout1 = V_CC / 2, PLL1_CP_GAIN = 3			–1600
I_CPout1%MIS	Charge pump Sink / source mismatch	V_CPout1 = V_CC / 2, T = 25°C			3%	10%
I_CPout1V_TUNE	Magnitude of charge pump current variation vs. charge pump voltage	0.5 V < V_CPout1 < V_CC – 0.5 V T_A = 25°C			4%
I_CPout1%TEMP	Charge pump current vs. temperature variation				4%
I_CPout1 TRI	Charge pump tri-state leakage current	0.5 V < V_CPout < V_CC – 0.5 V				5	nA
PN10kHz	PLL 1/f noise at 10-kHz offset. Normalized to 1-GHz output frequency	PLL1_CP_GAIN = 400 µA			–117		dBc/Hz
PN10kHz		PLL1_CP_GAIN = 1600 µA			–118		dBc/Hz
PN1Hz	Normalized phase noise contribution	PLL1_CP_GAIN = 400 µA			–221.5		dBc/Hz
PN1Hz	Normalized phase noise contribution	PLL1_CP_GAIN = 1600 µA			–223		dBc/Hz
PLL2 REFERENCE INPUT (OSCIN) SPECIFICATIONS
f_OSCin	PLL2 reference input ⁽⁷⁾					500	MHz
SLEW_OSCin	PLL2 Reference Clock minimum slew rate on OSCin ⁽³⁾	20% to 80%		0.15	0.5		V/ns
V_OSCin	Input voltage for OSCin or OSCin* ⁽³⁾	AC-coupled; single-ended (Unused pin AC-coupled to GND)		0.2		2.4	Vpp
V_IDOSCin	Differential voltage swing Figure 5	AC-coupled		0.2		1.55	\|V\|
V_SSOSCin	Differential voltage swing Figure 5	AC-coupled		0.4		3.1	Vpp
V_OSCin-offset	DC offset voltage between OSCin/OSCin* OSCinX* – OSCinX	Each pin AC-coupled			20		mV
f_{doubler_max}	Doubler input frequency ⁽³⁾	EN_PLL2_REF_2X = 1;⁽⁸⁾ OSCin Duty Cycle 40% to 60%				155	MHz
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
f_XTAL	Crystal frequency range ⁽³⁾	R_ESR < 40 Ω		6		20.5	MHz
P_XTAL	Crystal power dissipation ⁽⁹⁾	Vectron VXB1 crystal, 20.48 MHz, R_ESR < 40 Ω XTAL_LVL = 0			100		µW
C_IN	Input capacitance of LMK04816 OSCin port	-40 to +85°C			6		pF
PLL2 PHASE DETECTOR AND CHARGE-PUMP SPECIFICATIONS
f_PD2	Phase detector frequency					155	MHz
I_CPoutSOURCE	PLL2 charge pump source current ⁽⁶⁾	V_CPout2=V_CC / 2, PLL2_CP_GAIN = 0			100		µA
		V_CPout2=V_CC / 2, PLL2_CP_GAIN = 1			400
		V_CPout2=V_CC / 2, PLL2_CP_GAIN = 2			1600
		V_CPout2=V_CC / 2, PLL2_CP_GAIN = 3			3200
I_CPoutSINK	PLL2 charge pump sink current ⁽⁶⁾	V_CPout2=V_CC / 2, PLL2_CP_GAIN = 0			–100		µA
		V_CPout2=V_CC / 2, PLL2_CP_GAIN = 1			–400
		V_CPout2=V_CC / 2, PLL2_CP_GAIN = 2			–1600
		V_CPout2=V_CC / 2, PLL2_CP_GAIN = 3			–3200
I_CPout2%MIS	Charge pump sink and source mismatch	V_CPout2=V_CC / 2, T_A = 25 °C			3%	10%
I_CPout2V_TUNE	Magnitude of charge pump current vs. charge pump voltage variation	0.5 V < V_CPout2 < V_CC – 0.5 V T_A = 25°C			4%
I_CPout2%TEMP	Charge pump current vs. temperature variation				4%
I_CPout2TRI	Charge pump leakage	0.5 V < V_CPout2 < V_CC – 0.5 V				10	nA
PN10kHz	PLL 1/f noise at 10-kHz offset ⁽¹⁰⁾ Normalized to 1-GHz output frequency	PLL2_CP_GAIN = 400 µA			–118		dBc/Hz
PN10kHz		PLL2_CP_GAIN = 3200 µA			–121		dBc/Hz
PN1Hz	Normalized phase noise contribution ⁽¹¹⁾	PLL2_CP_GAIN = 400 µA			–222.5		dBc/Hz
PN1Hz	Normalized phase noise contribution ⁽¹¹⁾	PLL2_CP_GAIN = 3200 µA			–227		dBc/Hz
INTERNAL VCO SPECIFICATIONS
f_VCO	VCO tuning range	LMK04816		2370		2600	MHz
K_VCO	Fine tuning sensitivity	LMK04816	lower end of the tuning range		16		MHz/V
K_VCO	Fine tuning sensitivity	LMK04816	higher end of the tuning range		21		MHz/V
\|ΔT_CL\|	Allowable temperature drift for continuous lock ⁽¹²⁾ ⁽³⁾	After programming R30 for lock, no changes to output configuration are permitted to ensure continuous lock				125	°C
CLKOUT CLOSED-LOOP JITTER SPECIFICATIONS USING A COMMERCIAL QUALITY VCXO⁽¹³⁾
L(f)_CLKout	LMK04816 f_CLKout = 245.76 MHz SSB phase noise Measured at clock outputs Value is average for all output types ⁽¹⁴⁾	Offset = 1 kHz			–122.5		dBc/Hz
		Offset = 10 kHz			–132.9
		Offset = 100 kHz			–135.2
		Offset = 800 kHz			–143.9
		Offset = 10 MHz; LVDS			–156
		Offset = 10 MHz; LVPECL 1600 mVpp			–157.5
		Offset = 10 MHz; LVCMOS			–157.1
J_CLKout LVDS/LVPECL/LVCMOS	LMK04816⁽¹⁴⁾ f_CLKout = 245.76 MHz Integrated RMS jitter	BW = 12 kHz to 20 MHz			115		fs rms
J_CLKout LVDS/LVPECL/LVCMOS	LMK04816⁽¹⁴⁾ f_CLKout = 245.76 MHz Integrated RMS jitter	BW = 100 Hz to 20 MHz			123		fs rms
CLKOUT CLOSED-LOOP JITTER SPECIFICATIONS USING THE INTEGRATED LOW-NOISE CRYSTAL OSCILLATOR CIRCUIT⁽¹⁵⁾
	LMK04816 f_CLKout = 245.76 MHz Integrated RMS jitter	BW = 12 kHz to 20 MHz XTAL_LVL = 3			192		fs rms
	LMK04816 f_CLKout = 245.76 MHz Integrated RMS jitter	BW = 100 Hz to 20 MHz XTAL_LVL = 3			450		fs rms
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY
f_{CLKout-startup}	Default output clock frequency at device power-on ⁽¹⁶⁾	CLKout8, LVDS, LMK04816		90	98	110	MHz
CLOCK SKEW AND DELAY
\|T_SKEW\|	Maximum CLKoutX to CLKoutY ⁽¹⁷⁾ ⁽³⁾	LVDS-to-LVDS, T = 25°C, F_CLK = 800 MHz, R_L= 100 Ω AC coupled			30		ps
	Maximum CLKoutX to CLKoutY ⁽¹⁷⁾ ⁽³⁾	LVPECL-to-LVPECL, T = 25°C, F_CLK = 800 MHz, R_L= 100 Ω emitter resistors = 240 Ω to GND AC coupled			30
	Maximum skew between any two LVCMOS outputs, same CLKout or different CLKout ⁽¹⁷⁾ ⁽³⁾	R_L = 50 Ω, C_L = 5 pF, T = 25°C, F_CLK = 100 MHz. ⁽¹⁷⁾			100
MixedT_SKEW	LVDS or LVPECL to LVCMOS	Same device, T = 25 °C, 250 MHz			750		ps
td_0-DELAY	CLKin to CLKoutX delay ⁽¹⁷⁾	MODE = 2 PLL1_R_DLY = 0; PLL1_N_DLY = 0			1850		ps
td_0-DELAY	CLKin to CLKoutX delay ⁽¹⁷⁾	MODE = 2 PLL1_R_DLY = 0; PLL1_N_DLY = 0; VCO Frequency = 2457.6 MHz Analog delay select = 0; Feedback clock digital delay = 11; Feedback clock half step = 1; Output clock digital delay = 5; Output clock half step = 0;			0		ps
LVDS CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 1
f_CLKout	Maximum frequency ⁽³⁾ ⁽¹⁸⁾	R_L = 100 Ω		1536			MHz
V_OD	Differential output voltage Figure 6	T = 25°C, DC measurement AC-coupled to receiver input R = 100-Ω differential termination		250	400	450	\|mV\|
V_SS	Differential output voltage Figure 6			500	800	900	mVpp
ΔV_OD	Change in magnitude of V_OD for complementary output states			–50		50	mV
V_OS	Output offset voltage			1.125	1.25	1.375	V
ΔV_OS	Change in V_OS for complementary output states					35	\|mV\|
T_R / T_F	Output rise time	20% to 80%, RL = 100 Ω			200		ps
T_R / T_F	Output fall time	80% to 20%, RL = 100 Ω			200		ps
I_SA I_SB	Output short-circuit current - single-ended	Single-ended output shorted to GND, T = 25°C		–24		24	mA
I_SAB	Output short-circuit current - differential	Complimentary outputs tied together		–12		12	mA
LVPECL CLOCK OUTPUTS (CLKoutX)
f_CLKout	Maximum frequency ⁽³⁾ ⁽¹⁸⁾			1536			MHz
T_R / T_F	20% to 80% output rise	RL = 100-Ω, emitter resistors = 240 Ω to GND CLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp)			150		ps
T_R / T_F	80% to 20% output fall time				150		ps
700-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 2
V_OH	Output high voltage	T = 25°C, DC measurement Termination = 50 Ω to V_CC - 1.4 V			V_CC – 1.03		V
V_OL	Output low voltage				V_CC – 1.41		V
V_OD	Output voltage Figure 6			305	380	440	[mV]
V_SS	Output voltage Figure 6			610	760	880	mVpp
1200-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 3
V_OH	Output high voltage	T = 25°C, DC measurement Termination = 50 Ω to V_CC - 1.7 V			V_CC – 1.07		V
V_OL	Output low voltage				V_CC – 1.69		V
V_OD	Output voltage Figure 6			545	625	705	\|mV\|
V_SS	Output voltage Figure 6			1090	1250	1410	mVpp
1600-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 4
V_OH	Output high voltage	T = 25°C, DC Measurement Termination = 50 Ω to V_CC - 2.0 V			V_CC – 1.1		V
V_OL	Output low voltage				V_CC – 1.97		V
V_OD	Output voltage Figure 6			660	870	965	\|mV\|
V_SS	Output voltage Figure 6			1320	1740	1930	mVpp
2000-mVpp LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 5
V_OH	Output high voltage	T = 25°C, DC Measurement Termination = 50 Ω to V_CC – 2.3 V			V_CC – 1.13		V
V_OL	Output low voltage				V_CC – 2.2		V
V_OD	Output voltage Figure 6			800	1070	1200	\|mV\|
V_SS	Output voltage Figure 6			1600	2140	2400	mVpp
LVCMOS CLOCK OUTPUTS (CLKoutX)
f_CLKout	Maximum frequency ⁽³⁾ ⁽¹⁸⁾	5-pF Load		250			MHz
V_OH	Output high voltage	1-mA Load		V_CC – 0.1			V
V_OL	Output low voltage	1-mA Load				0.1	V
I_OH	Output high current (source)	V_CC = 3.3 V, V_O = 1.65 V			28		mA
I_OL	Output low current (sink)	V_CC = 3.3 V, V_O = 1.65 V			28		mA
DUTY_CLK	Output duty cycle ⁽³⁾	V_CC / 2 to V_CC / 2, F_CLK = 100 MHz, T = 25°C		45%	50%	55%
T_R	Output rise time	20% to 80%, RL = 50 Ω, CL = 5 pF			400		ps
T_F	Output fall time	80% to 20%, RL = 50 Ω, CL = 5 pF			400		ps
DIGITAL OUTPUTS (Status_CLKinX, Status_LD, Status_Holdover, SYNC)
V_OH	High-level output voltage	I_OH = –500 µA		V_CC – 0.4			V
V_OL	Low-level output voltage	I_OL = 500 µA				0.4	V
DIGITAL INPUTS (Status_CLKinX, SYNC)
V_IH	High-level input voltage			1.6		V_CC	V
V_IL	Low-level input voltage					0.4	V
I_IH	High-level input current V_IH = V_CC	Status_CLKinX_TYPE = 0 (High impedance)		–5		5	µA
		Status_CLKinX_TYPE = 1 (Pullup)		–5		5
		Status_CLKinX_TYPE = 2 (Pulldown)		10		80
I_IL	Low-level input current V_IL = 0 V	Status_CLKinX_TYPE = 0 (High impedance)		–5		5	µA
		Status_CLKinX_TYPE = 1 (Pullup)		–40		-5
		Status_CLKinX_TYPE = 2 (Pulldown)		–5		5
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire)
V_IH	High-level input voltage			1.6		V_CC	V
V_IL	Low-level input voltage					0.4	V
I_IH	High-level input current	V_IH = V_CC		5		25	µA
I_IL	Low-level input current	V_IL = 0		–5		5	µA

(1) Load conditions for output clocks: LVDS: 100 Ω differential. See applications section Current Consumption and Power Dissipation Calculations for Icc for specific part configuration and how to calculate Icc for a specific design.

(2) CLKin0, CLKin1, and CLKin2 maximum is ensured by characterization, production tested at 200 MHz.

(3) Ensured by characterization.

(4) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance begins to degrade as the clock input slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) are less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.

(5) See Differential Voltage Measurement Terminology for definition of V_ID and V_OD voltages.

(6) This parameter is programmable

(7) F_OSCin maximum frequency ensured by characterization. Production tested at 200 MHz.

(8) The EN_PLL2_REF_2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path.

(9) See Application Section discussion of Optional Crystal Oscillator Implementation (OSCin and OSCin*).

(10) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L_{PLL_flicker}(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L_{PLL_flicker}(10 kHz) - 20log(Fout / 1 GHz), where L_{PLL_flicker}(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L_{PLL_flicker}(f) it is important to be on the 10-dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L_{PLL_flicker}(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of L_{PLL_flicker}(f) and L_{PLL_flat}(f).

(11) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L_{PLL_flat}(f), is defined as: PN1HZ=L_{PLL_flat}(f) - 20log(N) - 10log(f_PDX). L_{PLL_flat}(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and f_PDX is the phase detector frequency of the synthesizer. L_{PLL_flat}(f) contributes to the total noise, L(f).

(12) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register, even to the same value, activates a frequency calibration routine. This implies the part works over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it is necessary to reload the R30 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of –40°C to 85°C without violating specifications.

(13) VCXO used is a 122.88 MHz Crystek CVHD-950-122.880.

(14) f_VCO = 2457.6 MHz, PLL1 parameters: EN_PLL2_REF_2X = 1, PLL2_R = 2, F_PD1 = 1.024 MHz, I_CP1 = 100 μA, loop bandwidth = 10 Hz. A 122.88 MHz Crystek CVHD-950–122.880. PLL2 parameters: PLL2_R = 1, F_PD2 = 122.88 MHz, I_CP2 = 3200 μA, C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, PLL2_C3_LF = 0, PLL2_R3_LF = 0, PLL2_C4_LF = 0, PLL2_R4_LF = 0, CLKoutX_Y_DIV = 10, and CLKoutX_ADLY_SEL = 0.

(15) Crystal used is a 20.48 MHz Vectron VXB1-1150-20M480 and Skyworks varactor diode, SMV-1249-074LF.

(16) CLKout6 and OSCout0 also oscillate at start-up at the frequency of the VCXO attached to OSCin port.

(17) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode.

(18) Refer to typical performance charts for output operation performance at higher frequencies than the minimum maximum output frequency.

6.6 Timing Requirements

See Figure 8

		MIN	UNIT
T_ECS	LE-to-clock setup time	25	ns
T_DCS	Data-to-clock setup time	25	ns
T_CDH	Clock-to-data hold time	8	ns
T_CWH	Clock pulse width high	25	ns
T_CWL	Clock pulse width low	25	ns
T_CES	Clock-to-LE setup time	25	ns
T_EWH	LE pulse width	25	ns
T_CR	Falling clock to readback time	25	ns

6.7 Typical Characteristics: Clock Output AC Charcteristics

Figure 1. LVDS V_OD vs Frequency

Figure 3. LVPECL With 120-Ω Emitter Resistors V_OD vs Frequency

Figure 2. LVPECL With 240-Ω Emitter Resistors V_OD vs Frequency