LMK04816

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Three input low-noise clock jitter cleaner with dual loop PLLs

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Product details

Parameters

Function Dual-loop PLL Number of outputs 12 RMS jitter (fs) 100 Output frequency (Min) (MHz) 0.22 Output frequency (Max) (MHz) 2600 Input type LVCMOS, LVDS, LVPECL Output type LVCMOS, LVDS, LVPECL Supply voltage (Min) (V) 3.15 Supply voltage (Max) (V) 3.45 Features 0 Delay Operating temperature range (C) -40 to 85 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

WQFN (NKD) 64 81 mm² 9 x 9 open-in-new Find other Clock jitter cleaners & synchronizers

Features

  • Ultralow RMS Jitter Performance
    • 100-fs RMS Jitter (12 kHz to 20 MHz)
    • 123-fs RMS Jitter (100 Hz to 20 MHz)
  • Dual-Loop PLLATINUM™ PLL Architecture
    • PLL1
      • Integrated Low-Noise Crystal Oscillator
        Circuit
      • Holdover Mode When Input Clocks are Lost
        • Automatic or Manual Triggering and
          Recovery
    • PLL2
      • Normalized 1-Hz PLL Noise Floor of
        –227 dBc/Hz
      • Phase Detector Rate Up to 155 MHz
      • OSCin Frequency-Doubler
      • Integrated Low-Noise VCO
      • VCO Frequency Ranges From 2370 MHz
        to 2600 MHz
  • Three Redundant Input Clocks With LOS
    • Automatic and Manual Switch-Over Modes
  • 50% Duty Cycle Output Divides, 1 to 1045 (Even
    and Odd)
  • LVPECL, LVDS, or LVCMOS Programmable
    Outputs
  • Precision Digital Delay, Fixed or Dynamically-
    Adjustable
  • 25-ps Step Analog Delay Control, Up to 575 ps
  • 1/2 Clock Distribution Period Step Digital Delay,
    up to 522 Steps
  • 13 Differential Outputs; up to 26 Single-Ended
    • Up to 5 VCXO and Crystal-Buffered Outputs
  • Clock Rates of Up to 2600 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-Mode: Dual PLL, Single PLL, and Clock
    Distribution
  • Industrial Temperature Range: –40°C to +85°C
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
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Description

The LMK04816 device is the industry’s highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual-loop PLLATINUM architecture enables 111-fs RMS jitter (12 kHz to 20 MHz) using a low-noise VCXO module or sub-200-fs RMS jitter (12 kHz to 20 MHz) using a low-cost external crystal and varactor diode.

The dual-loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

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Technical documentation

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Type Title Date
* Data sheet LMK04816 Three Input Low-Noise Clock Jitter Cleaner With Dual Loop PLLs datasheet (Rev. C) Jan. 14, 2016
Selection guide TI Components for Aerospace and Defense Guide (Rev. E) Mar. 22, 2017
Application note AN-1939 Crystal Based Oscillator Design with the LMK04000 Family (Rev. A) Apr. 26, 2013
User guide LMK04816 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs Jul. 02, 2012
User guide TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) Dec. 29, 2011
User guide Clock Conditioner Owner's Manual Nov. 10, 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
299
Description

The LMK04816 is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum™ architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using a low (...)

Features
  • Multi-mode: Dual PLL, single PLL, and clock distribution
  • Dual Loop PLLatinum PLL Architecture
    • PLL1
      • Holdover mode when input clocks are lost
        • Automatic or manual triggering/recovery
    • PLL2
      • Integrated Low-Noise VCO
  • 3 redundant input clocks with LOS
    • Automatic and manual switch-over modes
  • 50% duty cycle output (...)

Software development

APPLICATION SOFTWARE & FRAMEWORK Download
Clock Design Tool - Loop Filter & Device Configuration + Simulation
CLOCKDESIGNTOOL The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
APPLICATION SOFTWARE & FRAMEWORK Download
Texas Instruments Clocks and Synthesizers (TICS) Pro Software
TICSPRO-SW The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Features
  • Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
  • Export programming configurations for use in end application.
IDE, CONFIGURATION, COMPILER OR DEBUGGER Download
CodeLoader Software for device register programming
CODELOADER The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.


Which software do I use?

Product

Loop (...)

Design tools & simulation

SIMULATION MODEL Download
SNAM103C.ZIP (120 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
DESIGN TOOL Download
Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Features
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
  • Presents clear and intuitive block (...)

CAD/CAE symbols

Package Pins Download
WQFN (NKD) 64 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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