SNAS828A february   2022  – june 2023 LMK1D1208I

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Parameter Measurement Information
  10. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fail-Safe Input
      2. 9.3.2 Input Stage Configurability
      3. 9.3.3 Dual Output Bank
      4. 9.3.4 I2C
        1. 9.3.4.1 I2C Address Assignment
      5. 9.3.5 LVDS Output Termination
      6. 9.3.6 Input Termination
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Enable Control
      2. 9.4.2 Bank Input Selection
      3. 9.4.3 Bank Mute Control
      4. 9.4.4 Output Enable Control
      5. 9.4.5 Output Amplitude Selection
    5. 9.5 Programming
    6. 9.6 Register Maps
      1. 9.6.1 LMK1D1208I Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Supply Recommendations

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when jitter or phase noise is critical to applications.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must be placed close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends adding as many high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package. TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip power supply that isolates the high-frequency switching noises generated by the clock driver. These beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low DC resistance, because it is imperative to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper operation.

Figure 10-5 shows this recommended power-supply decoupling method.

GUID-E86D5EF5-9457-4A76-BFE7-3B1410E5E05C-low.gif Figure 10-5 Power Supply Decoupling