SNAS855C November   2023  – May 2024 LMKDB1108 , LMKDB1120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Double Termination
        2. 8.3.4.2 Programmable Output Slew Rate
        3. 8.3.4.3 Programmable Output Swing
        4. 8.3.4.4 Accurate Output Impedance
        5. 8.3.4.5 Programmable Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 Registers
    2. 9.2 LMKDB1108 Registers
    3. 9.3 LMKDB1204 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 LMKDB1120 Registers

Table 9-1 lists the memory-mapped registers for the LMKDB1120 registers. All register offset addresses not listed in Table 9-1 must be considered as reserved locations and the register contents must not be modified.

Table 9-1 LMKDB1120 Registers
Offset Acronym Register Name Section
0h R0 Output Enable Control for CLK16 through CLK19 Section 9.1.1
1h R1 Output Enable Control for CLK0 through CLK7 Section 9.1.2
2h R2 Output Enable Control for CLK8 through CLK15 Section 9.1.3
3h R3 OE Pin Readback for CLK5 through CLK12 Section 9.1.4
4h R4 AOD Enable Control and SBI_EN Readback Section 9.1.5
5h R5 Device Info Section 9.1.6
6h R6 Device Info (cont.) Section 9.1.7
7h R7 SMBus Byte Counter Section 9.1.8
8h R8 SBI Mask for CLK0 through CLK7 Section 9.1.9
9h R9 SBI Mask for CLK8 and CLK15 Section 9.1.10
Ah R10 SBI Mask for CLK16 and CLK19 Section 9.1.11
Bh R11 Output Slew Rate Select MSB for CLK0 through CLK7 Section 9.1.12
Ch R12 Output Slew Rate Select MSB for CLK8 through CLK15 Section 9.1.13
Dh R13 Output Slew Rate Select MSB for CLK16 through CLK19 Section 9.1.14
14h R20 Output Amplitude Section 9.1.15
15h R21 Input Configuration, Save Config in PD, SMB SDATA Monitoring, and LOS Readback Section 9.1.16
21h R33 SBI Mask Readback for CLK0 through CLK7 Section 9.1.17
22h R34 SBI Mask Readback for CLK8 through CLK15 Section 9.1.18
23h R35 SBI Mask Readback for CLK16 through CLK19 Section 9.1.19
26h R38 Non-clearable SMBUS Write Lock Section 9.1.20
27h R39 LOS Event Status and Clearable SMBus Write Lock Section 9.1.21
5Bh R91 Slew Rate Speed Options 1 and 2 Assignments Section 9.1.22
5Ch R92 Slew Rate Speed Options 3 and 4 Assignments Section 9.1.23
62h R98 Output Slew Rate Select LSB for CLK0 through CLK7 Section 9.1.24
63h R99 Output Slew Rate Select LSB for CLK8 through CLK15 Section 9.1.25
64h R100 Output Slew Rate Select LSB for CLK16 through CLK19 Section 9.1.26

Complex bit access types are encoded to fit into small table cells. Table 9-2 shows the codes that are used for access types in this section.

Table 9-2 LMKDB1120 Access Type Codes
Access Type Code Description
Read Type
R R Read
RC R
C		 Read
to Clear
Write Type
W W Write
W1C W
1C		 Write
1 to clear
WSC W Write
Reset or Default Value
-n Value after reset or the default value

9.1.1 R0 Register (Offset = 0h) [Reset = 78h]

R0 is shown in Table 9-3.

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Table 9-3 R0 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R 0h Reserved
6 CLK_EN_19 R/W 1h Output Enable for CLK19
0h = Output Disabled (low/low)
1h = Output Enabled
5 CLK_EN_18 R/W 1h Output Enable for CLK18
0h = Output Disabled (low/low)
1h = Output Enabled
4 CLK_EN_17 R/W 1h Output Enable for CLK17
0h = Output Disabled (low/low)
1h = Output Enabled
3 CLK_EN_16 R/W 1h Output Enable for CLK16
0h = Output Disabled (low/low)
1h = Output Enabled
2:0 RESERVED R 0h Reserved

9.1.2 R1 Register (Offset = 1h) [Reset = FFh]

R1 is shown in Table 9-4.

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Table 9-4 R1 Register Field Descriptions
Bit Field Type Reset Description
7 CLK_EN_7 R/W 1h Output Enable for CLK7
0h = Output Disabled (low/low)
1h = Output Enabled
6 CLK_EN_6 R/W 1h Output Enable for CLK6
0h = Output Disabled (low/low)
1h = Output Enabled
5 CLK_EN_5 R/W 1h Output Enable for CLK5
0h = Output Disabled (low/low)
1h = Output Enabled
4 CLK_EN_4 R/W 1h Output Enable for CLK4
0h = Output Disabled (low/low)
1h = Output Enabled
3 CLK_EN_3 R/W 1h Output Enable for CLK3
0h = Output Disabled (low/low)
1h = Output Enabled
2 CLK_EN_2 R/W 1h Output Enable for CLK2
0h = Output Disabled (low/low)
1h = Output Enabled
1 CLK_EN_1 R/W 1h Output Enable for CLK1
0h = Output Disabled (low/low)
1h = Output Enabled
0 CLK_EN_0 R/W 1h Output Enable for CLK0
0h = Output Disabled (low/low)
1h = Output Enabled

9.1.3 R2 Register (Offset = 2h) [Reset = FFh]

R2 is shown in Table 9-5.

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Table 9-5 R2 Register Field Descriptions
Bit Field Type Reset Description
7 CLK_EN_15 R/W 1h Output Enable for CLK15
0h = Output Disabled (low/low)
1h = Output Enabled
6 CLK_EN_14 R/W 1h Output Enable for CLK14
0h = Output Disabled (low/low)
1h = Output Enabled
5 CLK_EN_13 R/W 1h Output Enable for CLK13
0h = Output Disabled (low/low)
1h = Output Enabled
4 CLK_EN_12 R/W 1h Output Enable for CLK12
0h = Output Disabled (low/low)
1h = Output Enabled
3 CLK_EN_11 R/W 1h Output Enable for CLK11
0h = Output Disabled (low/low)
1h = Output Enabled
2 CLK_EN_10 R/W 1h Output Enable for CLK10
0h = Output Disabled (low/low)
1h = Output Enabled
1 CLK_EN_9 R/W 1h Output Enable for CLK9
0h = Output Disabled (low/low)
1h = Output Enabled
0 CLK_EN_8 R/W 1h Output Enable for CLK8
0h = Output Disabled (low/low)
1h = Output Enabled

9.1.4 R3 Register (Offset = 3h) [Reset = 00h]

R3 is shown in Table 9-6.

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Table 9-6 R3 Register Field Descriptions
Bit Field Type Reset Description
7 RB_OEb_12 R 0h Status of OEb12
6 RB_OEb_11 R 0h Status of OEb11
5 RB_OEb_10 R 0h Status of OEb10
4 RB_OEb_9 R 0h Status of OEb9
3 RB_OEb_8 R 0h Status of OEb8
2 RB_OEb_7 R 0h Status of OEb7
1 RB_OEb_6 R 0h Status of OEb6
0 RB_OEb_5 R 0h Status of OEb5

9.1.5 R4 Register (Offset = 4h) [Reset = 10h]

R4 is shown in Table 9-7.

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Table 9-7 R4 Register Field Descriptions
Bit Field Type Reset Description
7:5 RESERVED R 0h Reserved
4 BANK1_AOD_ENABLE R/W 1h Enable automatic output disable to low/low when LOS event is detected. Refer to section "Automatic Output Disable" for more information.
0h = Disabled
1h = Enabled
3:1 RESERVED R 0h Reserved
0 RB_SBI_ENQ R 0h Status of SBI_ENQ

9.1.6 R5 Register (Offset = 5h) [Reset = 0Ah]

R5 is shown in Table 9-8.

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Table 9-8 R5 Register Field Descriptions
Bit Field Type Reset Description
7:4 REV_ID R 0h Silicon revision
3:0 VENDOR_ID R Ah Vendor ID

9.1.7 R6 Register (Offset = 6h) [Reset = C9h]

R6 is shown in Table 9-9.

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Table 9-9 R6 Register Field Descriptions
Bit Field Type Reset Description
7:0 DEV_ID R C9h Device ID

9.1.8 R7 Register (Offset = 7h) [Reset = 07h]

R7 is shown in Table 9-10.

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Table 9-10 R7 Register Field Descriptions
Bit Field Type Reset Description
7:5 RESERVED R 0h Reserved
4:0 SMBUS_BC R/W 7h SMBus Block Read Byte Count

9.1.9 R8 Register (Offset = 8h) [Reset = 00h]

R8 is shown in Table 9-11.

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Table 9-11 R8 Register Field Descriptions
Bit Field Type Reset Description
7 SBI_MASK_7 R/W 0h Mask off Side-Band Disable for CLK7
6 SBI_MASK_6 R/W 0h Mask off Side-Band Disable for CLK6
5 SBI_MASK_5 R/W 0h Mask off Side-Band Disable for CLK5
4 SBI_MASK_4 R/W 0h Mask off Side-Band Disable for CLK4
3 SBI_MASK_3 R/W 0h Mask off Side-Band Disable for CLK3
2 SBI_MASK_2 R/W 0h Mask off Side-Band Disable for CLK2
1 SBI_MASK_1 R/W 0h Mask off Side-Band Disable for CLK1
0 SBI_MASK_0 R/W 0h Mask off Side-Band Disable for CLK0

9.1.10 R9 Register (Offset = 9h) [Reset = 00h]

R9 is shown in Table 9-12.

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Table 9-12 R9 Register Field Descriptions
Bit Field Type Reset Description
7 SBI_MASK_15 R/W 0h Mask off Side-Band Disable for CLK15
6 SBI_MASK_14 R/W 0h Mask off Side-Band Disable for CLK14
5 SBI_MASK_13 R/W 0h Mask off Side-Band Disable for CLK13
4 SBI_MASK_12 R/W 0h Mask off Side-Band Disable for CLK12
3 SBI_MASK_11 R/W 0h Mask off Side-Band Disable for CLK11
2 SBI_MASK_10 R/W 0h Mask off Side-Band Disable for CLK10
1 SBI_MASK_9 R/W 0h Mask off Side-Band Disable for CLK9
0 SBI_MASK_8 R/W 0h Mask off Side-Band Disable for CLK8

9.1.11 R10 Register (Offset = Ah) [Reset = 00h]

R10 is shown in Table 9-13.

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Table 9-13 R10 Register Field Descriptions
Bit Field Type Reset Description
7:4 RESERVED R 0h Reserved
3 SBI_MASK_19 R/W 0h Mask off Side-Band Disable for CLK19
2 SBI_MASK_18 R/W 0h Mask off Side-Band Disable for CLK18
1 SBI_MASK_17 R/W 0h Mask off Side-Band Disable for CLK17
0 SBI_MASK_16 R/W 0h Mask off Side-Band Disable for CLK16

9.1.12 R11 Register (Offset = Bh) [Reset = FFh]

R11 is shown in Table 9-14.

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Table 9-14 R11 Register Field Descriptions
Bit Field Type Reset Description
7 SLEWRATE_SEL_CLK7_MSB R/W 1h MSB CLK7 slew rate select
6 SLEWRATE_SEL_CLK6_MSB R/W 1h MSB CLK6 slew rate select
5 SLEWRATE_SEL_CLK5_MSB R/W 1h MSB CLK5 slew rate select
4 SLEWRATE_SEL_CLK4_MSB R/W 1h MSB CLK4 slew rate select
3 SLEWRATE_SEL_CLK3_MSB R/W 1h MSB CLK3 slew rate select
2 SLEWRATE_SEL_CLK2_MSB R/W 1h MSB CLK2 slew rate select
1 SLEWRATE_SEL_CLK1_MSB R/W 1h MSB CLK1 slew rate select
0 SLEWRATE_SEL_CLK0_MSB R/W 1h MSB CLK0 slew rate select

9.1.13 R12 Register (Offset = Ch) [Reset = FFh]

R12 is shown in Table 9-15.

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Table 9-15 R12 Register Field Descriptions
Bit Field Type Reset Description
7 SLEWRATE_SEL_CLK15_MSB R/W 1h MSB CLK15 slew rate select
6 SLEWRATE_SEL_CLK14_MSB R/W 1h MSB CLK14 slew rate select
5 SLEWRATE_SEL_CLK13_MSB R/W 1h MSB CLK13 slew rate select
4 SLEWRATE_SEL_CLK12_MSB R/W 1h MSB CLK12 slew rate select
3 SLEWRATE_SEL_CLK11_MSB R/W 1h MSB CLK11 slew rate select
2 SLEWRATE_SEL_CLK10_MSB R/W 1h MSB CLK10 slew rate select
1 SLEWRATE_SEL_CLK9_MSB R/W 1h MSB CLK9 slew rate select
0 SLEWRATE_SEL_CLK8_MSB R/W 1h MSB CLK8 slew rate select

9.1.14 R13 Register (Offset = Dh) [Reset = 0Fh]

R13 is shown in Table 9-16.

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Table 9-16 R13 Register Field Descriptions
Bit Field Type Reset Description
7:4 RESERVED R 0h Reserved
3 SLEWRATE_SEL_CLK19_MSB R/W 1h MSB CLK19 slew rate select
2 SLEWRATE_SEL_CLK18_MSB R/W 1h MSB CLK18 slew rate select
1 SLEWRATE_SEL_CLK17_MSB R/W 1h MSB CLK17 slew rate select
0 SLEWRATE_SEL_CLK16_MSB R/W 1h MSB CLK16 slew rate select

9.1.15 R20 Register (Offset = 14h) [Reset = 66h]

R20 is shown in Table 9-17.

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Table 9-17 R20 Register Field Descriptions
Bit Field Type Reset Description
7:4 AMP_1 R/W 6h Global Differential output Control = 0.6 V to approximately 1 V
25mV/step Default = 0.75 V
0h = 600 mV
1h = 625 mV
2h = 650 mV
3h = 675 mV
4h = 700 mV
5h = 725 mV
6h = 750 mV
7h = 775 mV
8h = 800 mV
9h = 825 mV
Ah = 850 mV
Bh = 875 mV
Ch = 900 mV
Dh = 925 mV
Eh = 950 mV
Fh = 975 mV
3:0 RESERVED R 0h Reserved

9.1.16 R21 Register (Offset = 15h) [Reset = 0Ch]

R21 is shown in Table 9-18.

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Table 9-18 R21 Register Field Descriptions
Bit Field Type Reset Description
7 RX1_EN_AC_INPUT R/W 0h Enable receiver bias when CLKIN is AC coupled
0h = DC Coupled Input
1h = AC Coupled Input
6 RX1_EN_RTERM_LSB R/W 0h Enable termination resistors on CLKIN1
0h = Input Termination R Disabled
1h = Input Termination R Enabled
5 RESERVED R 0h Reserved
4 RESERVED R 0h Reserved
3 PD_RESTOREB R/W 1h Save Configuration in Power Down 1'b0 : config cleared 1'b1: config saved
2 SDATA_TIMEOUT_EN R/W 1h Enable SMB SDATA time out monitoring
0h = Disable SDATA Time Out
1h = Enable SDATA Time Out
1 RESERVED R 0h Reserved
0 LOSb_RB R 0h Real time read back of loss detect block output
0h = LOS Event Detected
1h = LOS Event Not-Detected

9.1.17 R33 Register (Offset = 21h) [Reset = FFh]

R33 is shown in Table 9-19.

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Table 9-19 R33 Register Field Descriptions
Bit Field Type Reset Description
7 SBI_CLK_7 R 1h Readback of Side-Band Disable for CLK7
6 SBI_CLK_6 R 1h Readback of Side-Band Disable for CLK6
5 SBI_CLK_5 R 1h Readback of Side-Band Disable for CLK5
4 SBI_CLK_4 R 1h Readback of Side-Band Disable for CLK4
3 SBI_CLK_3 R 1h Readback of Side-Band Disable for CLK3
2 SBI_CLK_2 R 1h Readback of Side-Band Disable for CLK2
1 SBI_CLK_1 R 1h Readback of Side-Band Disable for CLK1
0 SBI_CLK_0 R 1h Readback of Side-Band Disable for CLK0

9.1.18 R34 Register (Offset = 22h) [Reset = FFh]

R34 is shown in Table 9-20.

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Table 9-20 R34 Register Field Descriptions
Bit Field Type Reset Description
7 SBI_CLK_15 R 1h Readback of Side-Band Disable for CLK15
6 SBI_CLK_14 R 1h Readback of Side-Band Disable for CLK14
5 SBI_CLK_13 R 1h Readback of Side-Band Disable for CLK13
4 SBI_CLK_12 R 1h Readback of Side-Band Disable for CLK12
3 SBI_CLK_11 R 1h Readback of Side-Band Disable for CLK11
2 SBI_CLK_10 R 1h Readback of Side-Band Disable for CLK10
1 SBI_CLK_9 R 1h Readback of Side-Band Disable for CLK9
0 SBI_CLK_8 R 1h Readback of Side-Band Disable for CLK8

9.1.19 R35 Register (Offset = 23h) [Reset = 0Fh]

R35 is shown in Table 9-21.

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Table 9-21 R35 Register Field Descriptions
Bit Field Type Reset Description
7:4 RESERVED R 0h Reserved
3 SBI_CLK_19 R 1h Readback of Side-Band Disable for CLK19
2 SBI_CLK_18 R 1h Readback of Side-Band Disable for CLK18
1 SBI_CLK_17 R 1h Readback of Side-Band Disable for CLK17
0 SBI_CLK_16 R 1h Readback of Side-Band Disable for CLK16

9.1.20 R38 Register (Offset = 26h) [Reset = 00h]

R38 is shown in Table 9-22.

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Table 9-22 R38 Register Field Descriptions
Bit Field Type Reset Description
7:1 RESERVED R 0h Reserved
0 WRITE_LOCK W1C 0h Non-clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can only be cleared by recycling power.
0h = SMBus Not locked for Writing
1h = SMBus Locked for Writing

9.1.21 R39 Register (Offset = 27h) [Reset = 00h]

R39 is shown in Table 9-23.

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Table 9-23 R39 Register Field Descriptions
Bit Field Type Reset Description
7:2 RESERVED R 0h Reserved
1 LOS_EVT R/WSC 0h LOS Event Status When high, indicates that a LOS event is detected. Can be cleared by writing a 1 to the bit.
0h = LOS Event Not-Detected
1h = LOS Event Detected
0 WRITE_LOCK_RW1C R/W 0h Clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can be cleared by writing a 1 to the bit.
0h = SMBus Not Locked for Writing
1h = SMBus locked for writing

9.1.22 R91 Register (Offset = 5Bh) [Reset = 00h]

R91 is shown in Table 9-24.

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Table 9-24 R91 Register Field Descriptions
Bit Field Type Reset Description
7:4 SLEWRATE_OPT_2 R/W 0h There are four register assignments each storing a slew rate value (chosen out of 16 available slew rate values). This register bits relate to the 2nd option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15
3:0 SLEWRATE_OPT_1 R/W 0h There are four register assignments each storing a slew rate value (chosen out of 16 available slew rate values). This register bits relate to the 1st option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15

9.1.23 R92 Register (Offset = 5Ch) [Reset = 00h]

R92 is shown in Table 9-25.

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Table 9-25 R92 Register Field Descriptions
Bit Field Type Reset Description
7:4 SLEWRATE_OPT_4 R/W 0h There are four register assignments each storing a slew rate value (chosen out of 16 available slew rate values). This register bits relate to the 4th option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15
3:0 SLEWRATE_OPT_3 R/W 0h There are four register assignments each storing a slew rate value (chosen out of 16 available slew rate values). This register bits relate to the 3rd option. Go to Programmable Output Slew Rate section for more information.
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15

9.1.24 R98 Register (Offset = 62h) [Reset = 00h]

R98 is shown in Table 9-26.

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Table 9-26 R98 Register Field Descriptions
Bit Field Type Reset Description
7 SLEWRATE_SEL_CLK7_LSB R/W 0h LSB CLK7 slew rate select
6 SLEWRATE_SEL_CLK6_LSB R/W 0h LSB CLK6 slew rate select
5 SLEWRATE_SEL_CLK5_LSB R/W 0h LSB CLK5 slew rate select
4 SLEWRATE_SEL_CLK4_LSB R/W 0h LSB CLK4 slew rate select
3 SLEWRATE_SEL_CLK3_LSB R/W 0h LSB CLK3 slew rate select
2 SLEWRATE_SEL_CLK2_LSB R/W 0h LSB CLK2 slew rate select
1 SLEWRATE_SEL_CLK1_LSB R/W 0h LSB CLK1 slew rate select
0 SLEWRATE_SEL_CLK0_LSB R/W 0h LSB CLK0 slew rate select

9.1.25 R99 Register (Offset = 63h) [Reset = 00h]

R99 is shown in Table 9-27.

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Table 9-27 R99 Register Field Descriptions
Bit Field Type Reset Description
7 SLEWRATE_SEL_CLK15_LSB R/W 0h LSB CLK15 slew rate select
6 SLEWRATE_SEL_CLK14_LSB R/W 0h LSB CLK14 slew rate select
5 SLEWRATE_SEL_CLK13_LSB R/W 0h LSB CLK13 slew rate select
4 SLEWRATE_SEL_CLK12_LSB R/W 0h LSB CLK12 slew rate select
3 SLEWRATE_SEL_CLK11_LSB R/W 0h LSB CLK11 slew rate select
2 SLEWRATE_SEL_CLK10_LSB R/W 0h LSB CLK10 slew rate select
1 SLEWRATE_SEL_CLK9_LSB R/W 0h LSB CLK9 slew rate select
0 SLEWRATE_SEL_CLK8_LSB R/W 0h LSB CLK8 slew rate select

9.1.26 R100 Register (Offset = 64h) [Reset = 00h]

R100 is shown in Table 9-28.

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Table 9-28 R100 Register Field Descriptions
Bit Field Type Reset Description
7:4 RESERVED R 0h Reserved
3 SLEWRATE_SEL_CLK19_LSB R/W 0h LSB CLK19 slew rate select
2 SLEWRATE_SEL_CLK18_LSB R/W 0h LSB CLK18 slew rate select
1 SLEWRATE_SEL_CLK17_LSB R/W 0h LSB CLK17 slew rate select
0 SLEWRATE_SEL_CLK16_LSB R/W 0h LSB CLK16 slew rate select