SNOSAY9G September   2008  – February 2016 LMP2021 , LMP2022

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions SC-70 and VSSOP references from LMP2021 pinout descriptions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: 2.5 V
    6. 6.6 Electrical Characteristics: 5 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 EMI Suppression
      2. 7.4.2 Input Voltage Noise
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Achieving Lower Noise With Filtering
      2. 8.1.2 Input Bias Current
      3. 8.1.3 Lowering the Input Bias Current
      4. 8.1.4 Sensor Impedance
      5. 8.1.5 Transient Response to Fast Inputs
      6. 8.1.6 Digital Acquisition Systems
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
    3. 11.3 Related Links
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

MIN MAX UNIT
VIN Differential –VS VS
Supply Voltage (VS = V+ – V−) 6.0 V
All Other Pins V+ + 0.3 V− − 0.3 V
Output Short-Circuit Duration to V+ or V−(3) 5 seconds
Junction Temperature(4) 150 °C
Soldering Information    Infrared or Convection (20 sec) 235 °C
Wave Soldering Lead Temperature (10 sec) 260 °C
Tstg Storage temperature range −65 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Package power dissipation should be observed.
(4) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
Machine model ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Temperature Range −40 125 °C
Supply Voltage (VS = V+ – V–) 2.2 5.5 V

6.4 Thermal Information

THERMAL METRIC(1) LMP2021, LMP2022 LMP2021 LMP2022 UNIT
D DBV DGK
8 PINS 5 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 106 164 217 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: 2.5 V(1)

Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 2.5 V, V− = 0 V, VCM = V+/2, RL >10 kΩ to V+/2.
PARAMETER TEST CONDITIONS MIN(3) TYP(2) MAX(3) UNIT
VOS Input Offset Voltage –5 –0.9 5 μV
–40°C ≤ TJ ≤ 125°C –10 10
TCVOS Input Offset Voltage Drift(4) –0.02 0.001 0.02 μV/°C
IB Input Bias Current –100 ±23 100 pA
–40°C ≤ TJ ≤ 125°C –300 300
IOS Input Offset Current –200 ±57 200 pA
–40°C ≤ TJ ≤ 125°C –250 250
CMRR Common Mode Rejection Ratio −0.2 V ≤ VCM ≤ 1.7 V, 0 V ≤ VCM ≤ 1.5 V 105 141 dB
−0.2 V ≤ VCM ≤ 1.7 V, 0 V ≤ VCM ≤ 1.5 V, –40°C ≤ TJ ≤ 125°C 102
CMVR Input Common-Mode Voltage Range Large Signal CMRR ≥ 105 dB −0.2 1.7 V
Large Signal CMRR ≥ 102 dB, –40°C ≤ TJ ≤ 125°C 0 1.5
EMIRR Electro-Magnetic Interference Rejection Ratio(3) IN+ and IN− VRF-PEAK = 100 mVP (−20 dBVP)
f = 400 MHz		 40 dB
VRF-PEAK = 100 mVP (−20 dBVP)
f = 900 MHz		 48
VRF-PEAK = 100 mVP (−20 dBVP)
f = 1800 MHz		 67
VRF-PEAK = 100 mVP (−20 dBVP)
f = 2400 MHz		 79
PSRR Power Supply Rejection Ratio 2.5 V ≤ V+ ≤ 5.5 V, VCM = 0 115 130 dB
2.5 V ≤ V+ ≤ 5.5 V, VCM = 0 , –40°C ≤ TJ ≤ 125°C 112
2.2 V ≤ V+ ≤ 5.5 V, VCM = 0 110 130
AVOL Large Signal Voltage Gain RL = 10 kΩ to V+/2, VOUT = 0.5 V to 2 V 124 150 dB
RL = 10 kΩ to V+/2, VOUT = 0.5 V to 2 V, –40°C ≤ TJ ≤ 125°C 119
RL = 2 kΩ to V+/2, VOUT = 0.5 V to 2 V 120 150
RL = 2 kΩ to V+/2, VOUT = 0.5 V to 2 V, –40°C ≤ TJ ≤ 125°C 115
VOUT Output Swing High RL = 10 kΩ to V+/2 38 50 mV
from either rail
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 70
RL = 2 kΩ to V+/2 62 85
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 115
Output Swing Low RL = 10 kΩ to V+/2 30 45
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 55
RL = 2 kΩ to V+/2 58 75
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 95
IOUT Linear Output Current
 Sourcing, VOUT = 2 V 30 50 mA
Sinking, VOUT = 0.5 V 30 50
IS Supply Current Per Amplifier 0.95 1.10 mA
Per Amplifier, –40°C ≤ TJ ≤ 125°C 1.37
SR Slew Rate(5) AV = +1, CL = 20 pF, RL = 10 kΩ
VO = 2 VPP		 2.5 V/μs
GBW Gain Bandwidth Product CL = 20 pF, RL = 10 kΩ 5 MHz
GM Gain Margin CL = 20 pF, RL = 10 kΩ 10 dB
ΦM Phase Margin CL = 20 pF, RL = 10 kΩ 60 deg
CIN Input Capacitance Common Mode 12 pF
Differential Mode 12
en Input-Referred Voltage Noise Density f = 0.1 kHz or 10 kHz, AV = 1000 11 nV/√Hz
f = 0.1 kHz or 10 kHz, AV = 100 15
Input-Referred Voltage Noise 0.1 Hz to 10 Hz 260 nVPP
0.01 Hz to 10 Hz 330
In Input-Referred Current Noise f = 1 kHz 350 fA/√Hz
tr Recovery time to 0.1%, RL = 10 kΩ, AV = −50,
VOUT = 1.25 VPP Step, Duration = 50 μs		 50 µs
CT Cross Talk LMP2022, f = 1 kHz 150 dB
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA.
(2) Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(3) All limits are specified by testing, statistical analysis or design.
(4) Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
(5) The number specified is the average of rising and falling slew rates and is measured at 90% to 10%.

6.6 Electrical Characteristics: 5 V(1)

Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+/2, RL > 10 kΩ to V+/2.
PARAMETER TEST CONDITIONS MIN(3) TYP(2) MAX(3) UNIT
VOS Input Offset Voltage –5 −0.4 5 μV
–40°C ≤ TJ ≤ 125°C –10 10
TCVOS Input Offset Voltage Drift(2) –0.02 −0.004 0.02 μV/°C
IB Input Bias Current –100 ±25 100 pA
–40°C ≤ TJ ≤ 125°C –300 300
IOS Input Offset Current –200 ±48 200 pA
–40°C ≤ TJ ≤ 125°C –250 250
CMRR Common Mode Rejection Ratio −0.2 V ≤ VCM ≤ 4.2 V, 0 V ≤ VCM ≤ 4.0 V 120 139 dB
−0.2 V ≤ VCM ≤ 4.2 V, 0 V ≤ VCM ≤ 4.0 V, –40°C ≤ TJ ≤ 125°C 115
CMVR Input Common-Mode Voltage Range Large Signal CMRR ≥ 120 dB –0.2 4.2 V
Large Signal CMRR ≥ 115 dB, –40°C ≤ TJ ≤ 125°C 0 4.0
EMIRR Electro-Magnetic Interference Rejection Ratio(3) IN+ and IN− VRF-PEAK = 100 mVP (−20 dBVP)
f = 400 MHz		 58 dB
VRF-PEAK = 100 mVP (−20 dBVP)
f = 900 MHz		 64
VRF-PEAK = 100 mVP (−20 dBVP)
f = 1800 MHz		 72
VRF-PEAK = 100 mVP (−20 dBVP)
f = 2400 MHz		 82
PSRR Power Supply Rejection Ratio 2.5 V ≤ V+ ≤ 5.5 V, VCM = 0 115 130 dB
2.5 V ≤ V+ ≤ 5.5 V, VCM = 0, –40°C ≤ TJ ≤ 125°C 112
2.2 V ≤ V+ ≤ 5.5 V, VCM = 0 110 130
AVOL Large Signal Voltage Gain RL = 10 kΩ to V+/2, VOUT = 0.5 V to 4.5 V 125 160 dB
RL = 10 kΩ to V+/2, VOUT = 0.5 V to 4.5 V, –40°C ≤ TJ ≤ 125°C 120
RL = 2 kΩ to V+/2, VOUT = 0.5 V to 4.5 V 123 160
RL = 2 kΩ to V+/2, VOUT = 0.5 V to 4.5 V, –40°C ≤ TJ ≤ 125°C 118
VOUT Output Swing High RL = 10 kΩ to V+/2 83 135 mV
from either rail
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 170
RL = 2 kΩ to V+/2 120 160
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 204
Output Swing Low RL = 10 kΩ to V+/2 65 80
RL = 10 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 105
RL = 2 kΩ to V+/2 103 125
RL = 2 kΩ to V+/2, –40°C ≤ TJ ≤ 125°C 158
IOUT Linear Output Current
 Sourcing, VOUT = 4.5 V 30 50 mA
Sinking, VOUT = 0.5 V 30 50
IS Supply Current Per Amplifier 1.1 1.25 mA
Per Amplifier, –40°C ≤ TJ ≤ 125°C 1.57
SR Slew Rate(4) AV = +1, CL = 20 pF, RL = 10 kΩ
VO = 2 VPP		 2.6 V/μs
GBW Gain Bandwidth Product CL = 20 pF, RL = 10 kΩ 5 MHz
GM Gain Margin CL = 20 pF, RL = 10 kΩ 10 dB
ΦM Phase Margin CL = 20 pF, RL = 10 kΩ 60 deg
CIN Input Capacitance Common Mode 12 pF
Differential Mode 12
en Input-Referred Voltage Noise Density f = 0.1 kHz or 10 kHz, AV= 1000 11 nV/√Hz
f = 0.1 kHz or 10 kHz, AV= 100 15
Input-Referred Voltage Noise 0.1 Hz to 10 Hz Noise 260 nVPP
0.01 Hz to 10 Hz Noise 330
In Input-Referred Current Noise f = 1 kHz 350 fA/√Hz
tr Input Overload Recovery time to 0.1%, RL = 10 kΩ, AV = −50,
VOUT = 2.5 VPP Step, Duration = 50 μs		 50 μs
CT Cross Talk LMP2022, f = 1 kHz 150 dB
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA.
(2) Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
(3) The EMI Rejection Ratio is defined as EMIRR = 20Log ( VRF-PEAK/ΔVOS).
(4) The number specified is the average of rising and falling slew rates and is measured at 90% to 10%.

6.7 Typical Characteristics

Unless otherwise noted: TA = 25°C, RL > 10 kΩ, VS= V+ – V–, VS= 5 V, VCM = VS/2.
LMP2021 LMP2022 30014912.gif Figure 1. Offset Voltage Distribution
LMP2021 LMP2022 30014913.gif Figure 3. Offset Voltage Distribution
LMP2021 LMP2022 30014905.gif Figure 5. Offset Voltage vs. Supply Voltage
LMP2021 LMP2022 30014962.png Figure 7. Input Bias Current vs. VCM
LMP2021 LMP2022 30014906.gif Figure 9. Offset Voltage vs. VCM
LMP2021 LMP2022 30014904.gif Figure 11. Supply Current vs. Supply Voltage (Per Amplifier)
LMP2021 LMP2022 30014922.gif Figure 13. Open Loop Frequency Response
LMP2021 LMP2022 30014923.gif Figure 15. Open Loop Frequency Response Over Temperature
LMP2021 LMP2022 30014932.gif Figure 17. EMIRR vs. Input Power
LMP2021 LMP2022 30014928.png Figure 19. Time Domain Input Voltage Noise
LMP2021 LMP2022 30014931.gif Figure 21. CMRR vs. Frequency
LMP2021 LMP2022 30014909.gif Figure 23. Output Swing High vs. Supply Voltage
LMP2021 LMP2022 30014908.gif Figure 25. Output Swing High vs. Supply Voltage
LMP2021 LMP2022 30014942.gif Figure 27. Overload Recovery Time
LMP2021 LMP2022 30014920.gif Figure 29. Large Signal Step Response
LMP2021 LMP2022 30014919.gif Figure 31. Large Signal Step Response
LMP2021 LMP2022 30014924.gif Figure 33. Output Voltage vs. Output Current
LMP2021 LMP2022 30014914.gif Figure 2. TCVOS Distribution
LMP2021 LMP2022 30014915.gif Figure 4. TCVOS Distribution
LMP2021 LMP2022 30014930.gif Figure 6. PSRR vs. Frequency
LMP2021 LMP2022 30014961.png Figure 8. Input Bias Current vs. VCM
LMP2021 LMP2022 30014907.gif Figure 10. Offset Voltage vs. VCM
LMP2021 LMP2022 30014926.gif Figure 12. Input Voltage Noise vs. Frequency
LMP2021 LMP2022 30014921.gif Figure 14. Open Loop Frequency Response
LMP2021 LMP2022 30014934.gif Figure 16. EMIRR vs. Frequency
LMP2021 LMP2022 30014933.gif Figure 18. EMIRR vs. Input Power
LMP2021 LMP2022 30014929.png Figure 20. Time Domain Input Voltage Noise
LMP2021 LMP2022 30014916.gif Figure 22. Slew Rate vs. Supply Voltage
LMP2021 LMP2022 30014911.gif Figure 24. Output Swing Low vs. Supply Voltage
LMP2021 LMP2022 30014910.gif Figure 26. Output Swing Low vs. Supply Voltage
LMP2021 LMP2022 30014943.gif Figure 28. Overload Recovery Time
LMP2021 LMP2022 30014918.gif Figure 30. Small Signal Step Response
LMP2021 LMP2022 30014917.gif Figure 32. Small Signal Step Response
LMP2021 LMP2022 30014973.gif Figure 34. Cross Talk Rejection Ratio vs. Frequency (LMP2022)