SNVS814B June   2012  – June 2019 LMR10530

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Descriptions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Ratings
    3. 6.3 Electrical Characteristics
    4. 6.4 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Frequency Foldback
      2. 7.3.2 Load Step Response
      3. 7.3.3 Output Overvoltage Protection
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Current Limit
      6. 7.3.6 Soft Start/Shutdown
      7. 7.3.7 Thermal Shutdown
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Custom Design With WEBENCH® Tools
        2. 8.2.1.2 Inductor Selection
        3. 8.2.1.3 Input Capacitor
        4. 8.2.1.4 Output Capacitor
        5. 8.2.1.5 Catch Diode
        6. 8.2.1.6 Output Voltage
        7. 8.2.1.7 Efficiency Estimation
      2. 8.2.2 Application Curve
      3. 8.2.3 Other System Examples
        1. 8.2.3.1 LMR10530X Design Example 1
        2. 8.2.3.2 LMR10530X Design Example 2
        3. 8.2.3.3 LMR10530Y Design Example 3
        4. 8.2.3.4 LMR10530Y Design Example 4
  9. Layout
    1. 9.1 Layout Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Load Step Response

The LMR10530 has a fixed internal loop compensation, which results in a small-signal loop bandwidth highly related to the output voltage level. In general, the loop bandwidth at low voltage is larger than at high voltage due to the increased overall loop gain. The limited bandwidth at high output voltage may pose a challenge when loop step response is concerned. In this case, one effective approach to improving loop step response is to add a feed-forward capacitor CFF) in the range of 27 nF to 100 nF in parallel with the upper feedback resistor (assuming the lower feedback resistor is 2 kΩ), as shown in Figure 21. The feedforward capacitor introduces a zero-pole pair which helps compensate the loop. The position of the zero-pole pair is a function of the feedback resistors and capacitor:

Equation 1. LMR10530 30167358.png
Equation 2. LMR10530 30167359.png

Note the factor in parenthesis is the ratio of the output voltage to the feedback voltage. As the output voltage gets close to 0.6V, the pole moves towards the zero, tending to cancel it out. Consequently, adding CFF will have less effect on the step response at lower output voltages.

As an example, Figure 23 shows that at the output voltage of 3.3 V, 47 nF of CFF can boost the loop bandwidth to 117kHz, from the original 23kHz as shown in Figure 22. Correspondingly, the responses to a load step between 0.3 A and 3 A without and with CFF are shown in Figure 24 and Figure 25 respectively. The higher loop bandwidth as a result of CFF reduces the total output excursion by more than half.

Aside from the above approach, increasing the output capacitance is generally also effective to reduce the excursion in output voltage caused by a load step. This approach remains valid for applications where the desired output voltages are close to the feedback voltage.

LMR10530 30167355.pngFigure 21. Adding a CFF Capacitor
LMR10530 30167337.pngFigure 22. Loop Gain and Phase Without CFF
LMR10530 30167345.pngFigure 24. Load Step Response Without CFF
LMR10530 30167338.pngFigure 23. Loop Gain and Phase With CFF
LMR10530 30167346.pngFigure 25. Load Step Response With CFF