SNOSAW3D September   2007  – August 2016 LMV641

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics: 2.7 V
    6. 6.6 DC Electrical Characteristics: 10 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Voltage and Low-Power Operation
      2. 7.3.2 Wide Bandwidth
      3. 7.3.3 Low Input Referred Noise
      4. 7.3.4 Ground Sensing and Rail-to-Rail Output
      5. 7.3.5 Small Size
    4. 7.4 Device Functional Modes
      1. 7.4.1 Stability of Op Amp Circuits
        1. 7.4.1.1 In The Loop Compensation
        2. 7.4.1.2 Compensation by External Resistor
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High-Gain, Low-Power Inverting Amplifiers
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Anisotropic Magnetoresistive Sensor
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Gain Error and Bandwidth Consideration if Using an Analog to Digital Converter
      3. 8.2.3 Voiceband Filter
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(7)
MIN MAX UNIT
Differential input VID ±0.3 ±0.3 V
Supply voltage (VS = V+ - V−) 13.2 V
Input and output pin voltage (V− −0.3) V+ +0.3 V
Junction temperature (2) 150 °C
Storage temperature, Tstg –65 150 °C

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), (1) ±2000 V
Machine model (MM) ±200
(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Temperature (2) –40 125 °C
Supply voltage (VS = V+ – V−) 2.7 12 V

6.4 Thermal Information

THERMAL METRIC(1) LMV641 UNIT
DBV (SOT-23) DCK (SC70) D (SOIC)
5 PINS 5 PINS 8 PINS
RθJA(2) Junction-to-ambient thermal resistance 325 456 166 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 178.1 121.8 93.6 °C/W
RθJB Junction-to-board thermal resistance 60.8 68.9 90.9 °C/W
ψJT Junction-to-top characterization parameter 57.7 5.3 38.4 °C/W
ψJB Junction-to-board characterization parameter 60.2 68.1 90.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 DC Electrical Characteristics: 2.7 V

Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 2.7 V, V− = 0 V, VO = VCM = V+/2, and RL > 1 MΩ.
PARAMETER TEST CONDITIONS MIN
(4)		 TYP
(3)		 MAX
(4)		 UNIT
VOS Input offset voltage TA = 25°C 30 500 µV
Temperature extremes 750
TC VOS Input offset average drift 0.1 µV/°C
IB Input bias current TA = 25°C (5) 75 95 nA
Temperature extremes 110
IOS Input offset current 0.9 5 nA
CMRR Common-mode rejection ratio 0 V ≤ VCM ≤ 1.7 V TA = 25°C (5) 89 114 dB
Temperature extremes 84
PSRR Power supply rejection ratio 2.7 V ≤ V+ ≤ 10 V, VCM = 0.5 TA = 25°C (5) 94.5 105 dB
Temperature extremes 92.5
2.7 V ≤ V+ ≤ 12 V, VCM = 0.5 TA = 25°C (5) 94 100
Temperature extremes 92
CMVR Input common-mode voltage range CMRR ≥ 80 dB TA = 25°C (5) 0 1.8 V
CMRR ≥ 68 dB Temperature extremes 0 1.8
AVOL Large signal voltage gain 0.3 V ≤ VO ≤ 2.4 V, RL = 2 kΩ to V+/2
 82 88 dB
0.4 V ≤ VO ≤ 2.3 V, RL = 2 kΩ to V+/2 78
0.3 V ≤ VO ≤ 2.4 V, RL = 10 kΩ to V+/2 TA = 25°C (5) 86 98
0.4 V ≤ VO ≤ 2.3 V, RL = 10 kΩ to V+/2 Temperature extremes 82
VO Output swing high RL = 2 kΩ to V+/2, VIN = 100 mV TA = 25°C (5) 42 58 mV from rail
Temperature extremes 68
RL = 10 kΩ to V+/2, VIN = 100 mV TA = 25°C (5) 22 35
Temperature extremes 40
Output swing low RL = 2 kΩ to V+/2, VIN = 100 mV TA = 25°C (5) 38 48
Temperature extremes 58
RL = 10 kΩ to V+/2, VIN = 100 mV 18 30
35
IOUT Sourcing and sinking output current VIN_DIFF = 100 mV to VO = V+/2 (6) Sourcing 22 mA
Sinking 25
IS Supply current TA = 25°C (5) 138 170 µA
Temperature extremes 220
SR Slew rate AV = 1, VO = 1 VPP Rising (10% to 90%) 2.3 V/µs
Falling (90% to 10%) 1.6
GBW Gain bandwidth product 10 MHz
en Input-referred voltage noise f = 1 kHz 14 nV/√Hz
in Input-referred current noise f = 1 kHz 0.15 pA/√Hz
THD Total harmonic distortion f = 1 kHz, AV = 2, RL = 2 kΩ 0.014%

6.6 DC Electrical Characteristics: 10 V

Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 10 V, V− = 0 V,VO = VCM = V+/2, and RL > 1 MΩ.
PARAMETER TEST CONDITIONS MIN
(4)		 TYP
(3)		 MAX
(4)		 UNIT
VOS Input offset voltage TA = 25°C (5) 5 500 µV
Temperature extremes 750
TC VOS Input offset average drift 0.1 µV/°C
IB Input bias current (5) TA = 25°C (5) 70 90 nA
Temperature extremes 105
IOS Input offset current 0.7 5 nA
CMRR Common-mode rejection ratio 0 V ≤ VCM ≤ 9 V TA = 25°C (5) 94 120 dB
Temperature extremes 90
PSRR Power supply rejection ratio 2.7 V ≤ V+ ≤ 10 V, VCM = 0.5 V TA = 25°C (5) 94.5 105 dB
Temperature extremes 92.5
2.7 V ≤ V+ ≤ 12 V, VCM = 0.5 V TA = 25°C (5) 94 100
Temperature extremes 92
CMVR Input common-mode voltage range CMRR ≥ 80 dB TA = 25°C (5) 0 9.1 V
CMRR ≥ 76 dB Temperature extremes 0 9.1
AVOL Large signal voltage gain 0.3 V ≤ VO ≤ 9.7 V, RL = 2 kΩ to V+/2
0.4 V ≤ VO ≤ 9.6 V, RL = 2 kΩ to V+/2		 TA = 25°C (5) 90 99 dB
Temperature extremes 85
0.3 V ≤ VO ≤ 9.7 V, RL = 10 kΩ to V+/2
0.4 V ≤ VO ≤ 9.6 V, RL = 10 kΩ to V+/2		 TA = 25°C (5) 97 104
Temperature extremes 92
VO Output Swing High RL = 2 kΩ to V+/2, VIN = 100 mV TA = 25°C (5) 68 95 mV from rail
Temperature extremes 125
RL = 10 kΩ to V+/2, VIN = 100 mV TA = 25°C (5) 37 55
Temperature extremes 65
Output Swing Low RL = 2 kΩ to V+/2, VIN = 100 mV TA = 25°C (5) 65 90
Temperature extremes 110
RL = 10 kΩ to V+/2, VIN = 100 mV TA = 25°C (5) 32 42
Temperature extremes 52
IOUT Sourcing and sinking output current VIN_DIFF = 100 mV
to VO = V+/2 (6)		 Sourcing 26 mA
Sinking 112
IS Supply current TA = 25°C (5) 158 190 µA
Temperature extremes 240
SR Slew rate AV = 1, VO = 2 V to 8 VPP Rising (10% to 90%) 2.6 V/µs
Falling (90% to 10%) 1.6
GBW Gain bandwidth product 10 MHz
en Input-referred voltage noise f = 1 kHz 14 nV/√Hz
in Input-referred current noise f = 1 kHz 0.15 pA/√Hz
THD Total harmonic distortion f = 1 kHz, AV = 2, RL = 2 kΩ 0.002%
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For ensured specifications and the test conditions, see the Electrical Characteristics Tables.
(2) The maximum power dissipation is a function of TJ(MAX, RθJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material.
(4) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using Statistical Quality Control (SQC) method.
(5) Positive current corresponds to current flowing into the device.
(6) The part is not short-circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output current curves are provided in Typical Characteristics and should be consulted before designing for heavy loads.
(7) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office / Distributors for availability and specifications.

6.7 Typical Characteristics

Unless otherwise specified, TA = 25°C, V+ = 10 V, V− = 0 V, VCM = VS/2.
LMV641 20203307.gif
Figure 1. Supply Current vs Supply Voltage
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Figure 3. Offset Voltage vs VCM
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Figure 5. Offset Voltage vs VCM
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Figure 7. Offset Voltage Distribution
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Figure 9. CMRR vs Frequency
LMV641 20203317.gif
Figure 11. Input Bias Current vs VCM
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Figure 13. Open-Loop Gain and Phase With Capacitive Load
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Figure 15. Open-Loop Gain and Phase With Resistive Load
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Figure 17. Input Referred Noise Voltage vs Frequency
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Figure 19. THD+N vs Frequency
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Figure 21. THD+N vs VOUT
LMV641 20203334.gif
Figure 23. Sourcing Current vs Supply Voltage
LMV641 20203331.gif
Figure 25. Sourcing Current vs VOUT
LMV641 20203333.gif
Figure 27. Sourcing Current vs VOUT
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Figure 29. Small-Signal Transient Response
LMV641 20203313.gif
Figure 31. Output Swing High vs Supply Voltage
LMV641 20203315.gif
Figure 33. Output Swing High vs Supply Voltage
LMV641 20203372.gif
Figure 35. Slew Rate vs Supply Voltage
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Figure 2. Offset Voltage vs Supply Voltage
LMV641 20203310.gif
Figure 4. Offset Voltage vs VCM
LMV641 20203312.gif
Figure 6. Offset Voltage vs VCM
LMV641 20203319.gif
Figure 8. Offset Voltage Distribution
LMV641 20203367.gif
Figure 10. PSRR vs Frequency
LMV641 20203318.gif
Figure 12. Input Bias Current vs VCM
LMV641 20203328.gif
Figure 14. Open-Loop Gain and Phase With Capacitive Load
LMV641 20203330.gif
Figure 16. Open-Loop Gain and Phase With Supply Voltage
LMV641 20203335.gif
Figure 18. Close Loop Output Impedance vs Frequency
LMV641 20203369.gif
Figure 20. THD+N vs Frequency
LMV641 20203371.gif
Figure 22. THD+N vs VOUT
LMV641 20203365.gif
Figure 24. Sinking Current vs Supply Voltage
LMV641 20203332.gif
Figure 26. Sinking Current vs VOUT
LMV641 20203324.gif
Figure 28. Large-Signal Transient
LMV641 20203323.gif
Figure 30. Small-Signal Transient Response
LMV641 20203314.gif
Figure 32. Output Swing Low vs Supply voltage
LMV641 20203316.gif
Figure 34. Output Swing Low and Supply Voltage