SNOS032I August 1999 – June 2016 LMV821-N , LMV822-N , LMV822-N-Q1 , LMV824-N , LMV824-N-Q1
PRODUCTION DATA.
The LMV821/LMV822/LMV824 bring performance and economy to low voltage / low power systems. With a 5 MHz unity-gain frequency and a specified 1.4 V/µs slew rate, the quiescent current is only 220 µA/amplifier (2.7 V). They provide rail-to-rail (R-to-R) output swing into heavy loads (600 Ω specified). The input common-mode voltage range includes ground, and the maximum input offset voltage is 3.5 mV.
The amplifier's differential inputs consist of a non-inverting input (+IN) and an inverting input (–IN). The amplifer amplifies only the difference in voltage between the two inpus, which is called the differential input voltage. The output voltage of the op-amp Vout is given by Equation 1:
where A_{OL} is the open-loop gain of the amplifier, typically around 100dB (100,000x, or 10uV per Volt).
This section covers the following design considerations:
1. Frequency and Phase Response Considerations
2. Unity-Gain Pulse Response Considerations
3. Input Bias Current Considerations
The relationship between open-loop frequency response and open-loop phase response determines the closed-loop stability performance (negative feedback). The open-loop phase response causes the feedback signal to shift towards becoming positive feedback, thus becoming unstable. The further the output phase angle is from the input phase angle, the more stable the negative feedback will operate. Phase Margin (φ_{m}) specifies this output-to-input phase relationship at the unity-gain crossover point. Zero degrees of phase-margin means that the input and output are completely in phase with each other and will sustain oscillation at the unity-gain frequency.
The AC tables show φ_{m} for a no load condition. But φ_{m} changes with load. The Gain and Phase margin vs Frequency plots in the curve section can be used to graphically determine the φ_{m} for various loaded conditions. To do this, examine the phase angle portion of the plot, find the phase margin point at the unity-gain frequency, and determine how far this point is from zero degree of phase-margin. The larger the phase-margin, the more stable the circuit operation.
The bandwidth is also affected by load. The graphs of Figure 33 and Figure 34 provide a quick look at how various loads affect the φ_{m} and the bandwidth of the LMV821/822/824 family. These graphs show capacitive loads reducing both φ_{m} and bandwidth, while resistive loads reduce the bandwidth but increase the φ_{m}. Notice how a 600Ω resistor can be added in parallel with 220 picofarads capacitance, to increase the φ_{m} 20°(approx.), but at the price of about a 100 kHz of bandwidth.
Overall, the LMV821/822/824 family provides good stability for loaded condition.
A pull-up resistor is well suited for increasing unity-gain, pulse response stability. For example, a 600 Ω pull-up resistor reduces the overshoot voltage by about 50%, when driving a 220 pF load. Figure 35 shows how to implement the pull-up resistor for more pulse response stability.
Higher capacitances can be driven by decreasing the value of the pull-up resistor, but its value shouldn't be reduced beyond the sinking capability of the part. An alternate approach is to use an isolation resistor as illustrated in Figure 36.
Figure 37 shows the resulting pulse response from a LMV824, while driving a 10,000 pF load through a 20Ω isolation resistor.
Input bias current (I_{B}) can develop a somewhat significant offset voltage. This offset is primarily due to I_{B} flowing through the negative feedback resistor, R_{F}. For example, if I_{B} is 90 nA (max @ room) and R_{F} is 100 kΩ, then an offset of 9 mV will be developed (V_{OS}= I_{B }x R_{F}).Using a compensation resistor (R_{C}), as shown in Figure 38, cancels out this affect. But the input offset current (I_{OS}) will still contribute to an offset voltage in the same manner - typically 0.05 mV at room temp.