SNAS866 December   2023 LMX1214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power-On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
      4. 6.3.4 AUXCLK Output
        1. 6.3.4.1 AUXCLKOUT Output Format
        2. 6.3.4.2 AUXCLK_DIV_PRE and AUXCLK_DIV Dividers
      5. 6.3.5 SYNC Input Pins
        1. 6.3.5.1 SYNC Pins Common-Mode Voltage
        2. 6.3.5.2 Windowing Feature
    4. 6.4 Device Functional Modes Configurations
      1. 6.4.1 Pin Mode Control
  8. 7 Application and Implementation
    1. 7.1 Applications Information
      1. 7.1.1 SYNC Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.5.2 Windowing Feature

The windowing feature can be used to internally calibrate the timing between the SYNC and CLKIN pins to optimize setup and hold timing and trim out any mismatches between the SYNC and CLKIN paths. This feature requires that the timing from the SYNC rising edge to the CLKIN rising edge is consistent. The timing from the SYNC rising edge to the CLKIN rising edges can be tracked with the rb_CLKPOS field. After the timing to the rising edge of the CLKIN pin is found, the SYNC rising edge can be internally adjusted with the SYNC_DLY and SYNC_DLY_STEP fields to optimize setup and hold times.

GUID-20231201-SS0I-MLGW-4DCC-V2SW5FCHWDRS-low.svg Figure 6-3 SYNC Internal Timing Adjustment
GUID-20231201-SS0I-Q7DK-RMV3-PLKJN3MFDVLK-low.svg Figure 6-4 Flowchart for Windowing Operation
Table 6-8 SYNC_DLY_STEP
INPUT FREQUENCY RECOMMENDED SYNC_DLY_STEP DELAY (ps)
1.4 GHz < fCLKIN ≤ 2.7 GHz 0 28
2.4 GHz < fCLKIN ≤ 4.7 GHz 1 15
3.1 GHz < fCLKIN ≤ 5.7 GHz 2 11
fCLKIN ≥ 4.5 GHz 3 8

For the windowing feature:

  1. The SYNC pins must be held high for a minimum time of 3/fCLKIN + 1.6 ns and only after this time rb_CLKPOS field is valid.
  2. If the user infers multiple valid SYNC_DLY values from rb_CLKPOS registers to avoid setup-hold violations, TI recommends to choose the lowest valid SYNC_DLY to minimize variation over temperature.

For SYNC operation:

  1. Only one SYNC pin rising edge is permitted per 75 input clock cycles
  2. SYNC must stay high for more than six clock cycles