SNVS686L March   2011  – June 2025 LMZ22005

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Synchronization Input
      2. 6.3.2 Output Overvoltage Protection
      3. 6.3.3 Current Limit
      4. 6.3.4 Thermal Protection
      5. 6.3.5 Prebiased Start-Up
    4. 6.4 Device Functional Modes
      1. 6.4.1 Discontinuous And Continuous Conduction Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Design Steps
        3. 7.2.2.3 Enable Divider, RENT, RENB, and RENH Selection
        4. 7.2.2.4 Output Voltage Selection
        5. 7.2.2.5 Soft-start Capacitor Selection
        6. 7.2.2.6 Tracking Supply Divider Option
        7. 7.2.2.7 CO Selection
        8. 7.2.2.8 CIN Selection
        9. 7.2.2.9 Discontinuous and Continuous Conduction Modes Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
      3. 7.4.3 Power Dissipation and Thermal Considerations
      4. 7.4.4 Power Module SMT Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Thermal Information

THERMAL METRIC(1)LMZ22005UNIT
NDW (TO-PMOD)
7 PINS
RθJAJunction-to-ambient thermal resistance(2)4-layer Evaluation Printed-Circuit-Board,
60 vias, No air flow		19.3°C/W
2-layer JEDEC Printed-Circuit-Board,
No air flow		21.5
RθJC(top)Junction-to-case (top) thermal resistanceNo air flow1.9°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) Theta JA measured on a 3.5-in × 3.5-in 4-layer board, with 3-oz. copper on outer layers and 2-oz. copper on inner layers, sixty thermal vias, no air flow, and 1-W power dissipation. Refer to application note layout diagrams.