8.2.2.1 Design Steps

The LMZ23605 is fully supported by WEBENCH which offers: component selection, electrical and thermal simulations. Additionally there are both evaluation and demonstration boards that may be used as a starting point for design. The following list of steps can be used to manually design the LMZ23605 application.

All references to values refer to the Figure 49.

1. Select minimum operating V_IN with enable divider resistors
2. Program V_O with resistor divider selection
3. Select C_O
4. Select C_IN
5. Determine module power dissipation
6. Layout PCB for required thermal performance

8.2.2.2 Enable Divider, R_ENT, R_ENB and R_ENH Selection

Internal to the module is a 2-MΩ pullup resistor connected from V_IN to Enable. For applications not requiring precision undervoltage lockout (UVLO), the Enable input may be left open circuit and the internal resistor will always enable the module. In such case, the internal UVLO occurs typically at 4.3 V (V_INrising).

In applications with separate supervisory circuits Enable can be directly interfaced to a logic source. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ23605 output rail.

Enable provides a precise 1.279-V threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as V_IN. Additionally there is 21 μA (typical) of switched offset current allowing programmable hysteresis. See Figure 50.

The function of the enable divider is to allow the designer to choose an input voltage below which the circuit will be disabled. This implements the feature of programmable UVLO. The two resistors must be chosen based on the following ratio:

The LMZ23605 typical application shows 12.7 kΩ for R_ENB and 42.2 kΩ for R_ENT resulting in a rising UVLO of 5.46 V. This divider presents 8.33 V to the input when the divider is raised to 36 V which would exceed the recommended 5.5-V limit for Enable. A midpoint 5.1-V Zener clamp is applied to allow the application to cover the full 6 V to 36 V range of operation. The Zener clamp is not required if the target application prohibits the maximum Enable input voltage from being exceeded.

Additional enable voltage hysteresis can be added with the inclusion of R_ENH. It is possible to select values for R_ENT and R_ENB such that R_ENH is a value of zero allowing it to be omitted from the design.

Rising threshold can be calculated as follows:

Whereas the falling threshold level can be calculated using:

Figure 50. Enable input detail

8.2.2.3 Output Voltage Selection

Output voltage is determined by a divider of two resistors connected between V_O and ground. The midpoint of the divider is connected to the FB input.

The regulated output voltage determined by the external divider resistors R_FBT and R_FBB is:

Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:

These resistors must generally be chosen from values in the range of 1.0 kΩ to 10.0 kΩ.

For V_O = 0.8 V the FB pin can be connected to the output directly and R_FBB can be set to 8.06 kΩ to provide minimum output load.

Table 1 lists the values for R_FBT and R_FBB.

8.2.2.4 Soft-Start Capacitor Selection

Programmable soft-start permits the regulator to slowly ramp to its steady-state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time.

Upon turnon, after all UVLO conditions have been passed, an internal 1.6-ms circuit slowly ramps the SS/TRK input to implement internal soft-start. If 2 ms is an adequate turnon time then the Css capacitor can be left unpopulated. Longer soft-start periods are achieved by adding an external capacitor to this input.

Soft-start duration is given by the formula:

This equation can be rearranged as follows:

Using a 0.22-μF capacitor results in 3.5 ms typical soft-start duration; and 0.47 μF results in 7.5 ms typical. 0.47 μF is a recommended initial value.

As the soft-start input exceeds 0.796 V the output of the power stage will be in regulation and the 50-μA current is deactivated. The following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal current sink.

• The Enable input being pulled low
• Thermal shutdown condition
• Internal V_CC UVLO (Approx 4.3-V input to V_IN)

8.2.2.5 C_O Selection

None of the required C_O output capacitance is contained within the module. A minimum value of 200 μF is required based on the values of internal compensation in the error amplifier. Low ESR tantalum, organic semiconductor or specialty polymer capacitor types are recommended for obtaining lowest ripple. The output capacitor C_O may consist of several capacitors in parallel placed in close proximity to the module. The output capacitor assembly must also meet the worst case minimum ripple current rating of 0.5 × I_{LR P-P}, as calculated in Equation 14 below. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit it. Loop response verification is also valuable to confirm closed loop behavior.

For applications with dynamic load steps; the following equation provides a good first pass approximation of C_O for load transient requirements. Where V_O-Tran is 100 mV on a 3.3-V output design.

Solving:

One recommended output capacitor combination is a 220-µF, 7-mΩ ESR specialty polymer cap in parallel with a 100-µF 6.3-V X5R ceramic. This combination provides excellent performance that may exceed the requirements of certain applications. Additionally some small ceramic capacitors can be used for high frequency EMI suppression.

8.2.2.6 C_IN Selection

The LMZ23605 module contains a small amount of internal ceramic input capacitors. Additional input capacitance is required external to the module to handle the input ripple current of the application. The input capacitor can be several capacitors in parallel. This input capacitance must be located in very close proximity to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Input ripple current rating is dictated by the equation:

As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when V_IN = 2 × V_O

Recommended minimum input capacitance is 22uF X7R (or X5R) ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. It is also recommended that attention be paid to the voltage and temperature derating of the capacitor selected.

If the system design requires a certain minimum value of peak-to-peak input ripple voltage (ΔV_IN) be maintained then the following equation may be used.

If ΔV_IN is 1% of V_IN for a 12-V input to 3.3-V output application this equals 120 mV and f_SW = 812 kHz.

Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines. The LMZ23605 typical applications schematic and evaluation board include a 150-μF 50-V aluminum capacitor for this function. There are many situations where this capacitor is not necessary.

8.2.2.7 Discontinuous Conduction and Continuous Conduction Mode Selection

The approximate formula for determining the DCM/CCM boundary is as follows:

The inductor internal to the module is 3.3 μH. This value was chosen as a good balance between low and high input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple current (I_LR). I_LR can be calculated with:

If the output current I_O is determined by assuming that I_O = I_L, the higher and lower peak of I_LR can be determined.