SLVSBV8E June   2013  – February 2020 LMZ31704

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Application
  4. 4 Revision History
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Package Specifications
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
  6. 6 Device Information
    1. 6.1 Functional Block Diagram
    2.     Pin Functions
  7. 7 Typical Characteristics (PVIN = VIN = 12 V)
  8. 8 Typical Characteristics (PVIN = VIN = 5 V)
  9. 9 Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)
  10. 10Application Information
    1. 10.1  Adjusting the Output Voltage
    2. 10.2  Capacitor Recommendations for the LMZ31704 Power Supply
      1. 10.2.1 Capacitor Technologies
        1. 10.2.1.1 Electrolytic, Polymer-Electrolytic Capacitors
        2. 10.2.1.2 Ceramic Capacitors
        3. 10.2.1.3 Tantalum, Polymer-Tantalum Capacitors
      2. 10.2.2 Input Capacitor
      3. 10.2.3 Output Capacitor
    3. 10.3  Transient Response
    4. 10.4  Transient Waveforms
    5. 10.5  Application Schematics
    6. 10.6  Custom Design With WEBENCH® Tools
    7. 10.7  VIN and PVIN Input Voltage
    8. 10.8  3.3 V PVIN Operation
    9. 10.9  Power Good (PWRGD)
    10. 10.10 SYNC_OUT
    11. 10.11 Parallel Operation
    12. 10.12 Light Load Efficiency (LLE)
    13. 10.13 Power-Up Characteristics
    14. 10.14 Pre-Biased Start-up
    15. 10.15 Remote Sense
    16. 10.16 Thermal Shutdown
    17. 10.17 Output On/Off Inhibit (INH)
    18. 10.18 Slow Start (SS/TR)
    19. 10.19 Overcurrent Protection
    20. 10.20 Synchronization (CLK)
    21. 10.21 Sequencing (SS/TR)
    22. 10.22 Programmable Undervoltage Lockout (UVLO)
    23. 10.23 Layout Considerations
    24. 10.24 EMI
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.23 Layout Considerations

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 42 through Figure 45 shows a typical PCB layout. Some considerations for an optimized layout are:

  • Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
  • Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
  • Locate additional output capacitors between the ceramic capacitor and the load.
  • Keep AGND and PGND separate from one another.
  • Place RSET, RRT, and CSS as close as possible to their respective pins.
  • Use multiple vias to connect the power planes to internal layers.
LMZ31704 Layout Top.pngFigure 42. Typical Top-Layer Layout
LMZ31704 Layout L3.pngFigure 44. Typical Layer-3 Layout
LMZ31704 Layout Layer2.pngFigure 43. Typical Layer-2 Layout
LMZ31704 Layout Bot.pngFigure 45. Typical Bottom-Layer Layout