SNVS096E Data sheet

SNVS096E June 1999 – July 2016 LP2954 , LP2954A

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

D|8
- MSOI002K
KTT|3
- MPSF006E
NDE|3
- MMSF014

Thermal pad, mechanical data (Package|Pins)

KTT|3
- PPTD276A

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽²⁾⁽¹⁾

	MIN	MAX	UNIT
Input supply voltage	–20	30	V
Power dissipation⁽²⁾	Internally Limited
Storage temperature, T_stg	–65	150	°C

(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(2) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heat sink values (if a heat sink is used). If power dissipation causes the junction temperature to exceed specified limits, the device goes into thermal shutdown.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Operating junction temperature		–40		125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LP2954, LP2954A			UNIT
		KTT (DDPAK/TO-263)	NDE (TO-220)	D (SOIC)
		3 PINS	3 PINS	8 PINS
R_θJA⁽²⁾	Junction-to-ambient thermal resistance, High-K	44.3	80.3⁽³⁾	105.0	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	44.8	38.6	47.3	°C/W
R_θJB	Junction-to-board thermal resistance	23.8	73.1	45.8	°C/W
ψ_JT	Junction-to-top characterization parameter	10.6	13.5	6.2	°C/W
ψ_JB	Junction-to-board characterization parameter	22.7	73.1	45.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.0	0.9	—	°C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) Thermal resistance value R_θJA is based on the EIA/JEDEC High-K printed circuit board defined by JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

(3) The TO-220 (NDE) package is vertically mounted in center of JEDEC High-K test board (JESD 51-7) with no additional heat sink. This is a through-hole package; this is NOT a surface mount package.

6.5 Electrical Characteristics

Limits are specified by production testing or correlation techniques using standard Statistical Quality Control (SQC) methods. Unless otherwise noted: T_J = 25°C, V_IN = 6 V, I_L = 1 mA, C_L = 2.2 μF

PARAMETER		TEST CONDITIONS	LP2954AI			LP2954I			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
V_O	Output voltage⁽¹⁾		4.975	5	5.025	4.95	5	5.05	V
		−40°C to 125°C	4.94		5.06	4.9		5.1
		1 mA ≤ I_L ≤ 250 mA		5			5
		1 mA ≤ I_L ≤ 250 mA −40°C to 125°C	4.93		5.07	4.88		5.12
ΔV_O/ΔT	Output voltage temperature coefficient	See⁽²⁾, –40°C ≤ T_J ≤ 125°C		20	100		20	150	ppm/°C
ΔV_O/V_O	Line regulation	V_IN = 6 V to 30 V		0.03%	0.1%		0.03%	0.2%
ΔV_O/V_O	Line regulation	V_IN = 6 V to 30 V –40°C ≤ T_J ≤ 125°C			0.2%			0.3%
ΔV_O/V_O	Load regulation	I_L = 1 to 250 mA I_L = 0.1 to 1 mA⁽³⁾		0.04%	0.16%		0.04%	0.2%
ΔV_O/V_O	Load regulation	I_L = 1 to 250 mA I_L = 0.1 to 1 mA –40°C ≤ T_J ≤ 125°C			0.2%			0.3%
V_IN – V_O	Dropout voltage⁽⁴⁾	I_L = 1 mA		60	100		60	100	mV
		I_L = 1 mA –40°C ≤ T_J ≤ 125°C			150			150
		I_L = 50 mA		240	300		240	300
		I_L = 50 mA, –40°C ≤ T_J ≤ 125°C			420			420
		I_L = 100 mA		310	400		310	400
		I_L = 100 mA –40°C ≤ T_J ≤ 125°C			520			520
		I_L = 250 mA		470	600		470	600
		I_L = 250 mA –40°C ≤ T_J ≤ 125°C			800			800
I_GND	Ground pin current⁽⁵⁾	I_L = 1 mA		90	150		90	150	µA
		I_L = 1 mA –40°C ≤ T_J ≤ 125°C			180			180	µA
		I_L = 50 mA		1.1	2		1.1	2	mA
		I_L = 50 mA –40°C ≤ T_J ≤ 125°C			2.5			2.5
		I_L = 100 mA		4.5	6		4.5	6
		I_L = 100 mA –40°C ≤ T_J ≤ 125°C			8			8
		I_L = 250 mA		21	28		21	28
		I_L = 250 mA –40°C ≤ T_J ≤ 125°C			33			33
I_GND	Ground pin current at dropout⁽⁵⁾	V_IN = 4.5 V		120	170		120	170	µA
I_GND	Ground pin current at dropout⁽⁵⁾	V_IN = 4.5 V –40°C ≤ T_J ≤ 125°C			210			210	µA
I_LIMIT	Current limit	V_O = 0 V		380	500		380	500	mA
I_LIMIT	Current limit	V_O = 0 V –40°C ≤ T_J ≤ 125°C			530			530	mA
ΔV_O/ΔP_D	Thermal regulation	See⁽⁶⁾		0.05	0.2		0.05	0.2	%/W
e_n	Output noise 10 Hz to 100 kHz	I_L = 100 mA, C_L = 2.2 µF		400			400		μV_RMS
		I_L = 100 mA, C_L = 33 µF		260			260
		I_L = 100 mA, C_L = 33 µF⁽⁷⁾		80			80
ADDITIONAL SPECIFICATIONS FOR THE ADJUSTABLE DEVICE (LP2954AIM and LP2954IM)
V_REF	Reference voltage	See⁽⁸⁾	1.215	1.23	1.245	1.205	1.23	1.255	V
V_REF	Reference voltage	See⁽⁸⁾ –40°C ≤ T_J ≤ 125°C	1.205		1.255	1.19		1.27	V
ΔV_REF/ V_REF	Reference voltage line regulation	V_IN= 2.5 V to V_O(NOM) + 1 V		0.03%	0.1%		0.03%	0.2%
ΔV_REF/ V_REF	Reference voltage line regulation	V_IN= 2.5 V to V_O(NOM) +1 V to 30 V⁽⁹⁾⁽⁸⁾–40°C ≤ T_J ≤ 125°C			0.2%			0.4%
ΔV_REF/ΔT	Reference voltage temperature coefficient	See⁽²⁾ –40°C ≤ T_J ≤ 125°C		20					ppm/°C
I_B(FB)	Feedback pin bias current			20	40		20	40	nA
I_B(FB)	Feedback pin bias current	–40°C ≤ T_J ≤ 125°C			60			60	nA
I_GND	Ground pin current at shutdown⁽⁵⁾	V_SHUTDOWN≤ 1.1 V		105	140		105	140	μA
I_O(SINK)	Output OFF pulldown current	See⁽¹⁰⁾	30			30			mA
I_O(SINK)	Output OFF pulldown current	See⁽¹⁰⁾ –40°C ≤ T_J ≤ 125°C	20			20
DROPOUT DETECTION COMPARATOR
I_OH	Output HIGH leakage current	V_OH = 30 V		0.01	1		0.01	1	µA
I_OH	Output HIGH leakage current	V_OH = 30 V, –40°C ≤ T_J ≤ 125°C			2			2	µA
V_OL	Output LOW voltage	V_IN = V_O(NOM) − 0.5 V I_O(COMP) = 400 μA –40°C ≤ T_J ≤ 125°C		150	250		150	250	mV
V_OL	Output LOW voltage				400			400	mV
V_THR(MAX)	Upper threshold voltage	See⁽¹¹⁾	–80	–60	–35	–80	–60	–35	mV
V_THR(MAX)	Upper threshold voltage	See⁽¹¹⁾ –40°C ≤ T_J ≤ 125°C	–95		–25	–95		–25	mV
V_THR(MIN)	Lower threshold voltage	See⁽¹¹⁾	–110	–85	–55	–110	–85	–55	mV
V_THR(MIN)	Lower threshold voltage	See⁽¹¹⁾ –40°C ≤ T_J ≤ 125°C	–160		–40	–160		–40	mV
HYST	Hysteresis	See⁽¹¹⁾		15			15		mV
SHUTDOWN INPUT
V_OS	Input offset voltage	(Referred to V_REF)	−7.5	±3	7.5	−7.5	±3	7.5	mV
V_OS	Input offset voltage	(Referred to V_REF), –40°C ≤ T_J ≤ 125°C	–10		10	–10		10	mV
HYST	Hysteresis			6			6		mV
I_B	Input bias current	V_IN(SHUTDOWN) = 0 V to 5 V	–30	10	30	–30	10	30	nA
I_B	Input bias current	V_IN(SHUTDOWN) = 0 V to 5 V, –40°C ≤ T_J ≤ 125°C	–50		50	–50		50	nA

(1) When used in dual-supply systems where the regulator load is returned to a negative supply, the output voltage must be diode-clamped to ground.

(2) Output voltage temperature coefficient is defined as the worst-case voltage change divided by the total temperature range.

(3) Regulation is measured at constant junction temperature using low duty cycle pulse testing. Parts are tested separately for load regulation in the load ranges 0.1 mA to 1 mA and 1 mAto 250 mA. Changes in output voltage due to heating effects are covered by the thermal regulation specification.

(4) Dropout voltage is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential.

(5) GND pin current is the regulator quiescent current. The total current drawn from the source is the sum of the load current plus the GND pin current.

(6) Thermal regulation is defined as the change in output voltage at a time T after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for 200-mA load pulse at V_IN = 20 V (3-W pulse) for T = 10 ms.

(7) Connect a 0.1-μF capacitor from the OUT pin to the FEEDBACK pin.

(8) V_REF ≤ V_OUT ≤ (V_IN − 1 V), 2.3 V ≤ V_IN ≤ 30 V, 100 μA ≤ I_L≤ 250 mA.

(9) Two separate tests are performed, one covering V_IN = 2.5 V to V_O(NOM) + 1 V and the other test for V_IN = 2.5 V to V_O(NOM) + 1 V to 30 V.

(10) V_SHUTDOWN ≤ 1.1 V, V_OUT = V_O(NOM).

(11) Comparator thresholds are expressed in terms of a voltage differential at the FEEDBACK pin below the nominal reference voltage measured at V_IN = V_O(NOM) + 1 V. To express these thresholds in terms of output voltage change, multiply by the error amplifier gain, which is V_OUT/V_REF = (R1 + R2 ) / R2.