SNVS171K November   2001  – December 2023 LP2992

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Information
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Output Pulldown
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Estimating Junction Temperature
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Noise Bypass Capacitor (CBYPASS)
      4. 7.1.4 Power Dissipation (PD)
      5. 7.1.5 Recommended Capacitor Types
      6. 7.1.6 Reverse Current
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 ON/OFF Operation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • VIN range (new chip): 2.5 V to 16 V
  • VOUT range (new chip):
    • 1.2 V to 5.0 V (fixed, 100-mV steps)
  • VOUT accuracy:
    • ±1% for A-grade legacy chip
    • ±1.5% for standard-grade legacy chip
    • ±0.5% for new chip only
  • ±1% output accuracy over load, and temperature for new chip
  • Output current: Up to 250 mA
  • Low IQ (new chip): 69 μA at ILOAD = 0 mA
  • Low IQ (new chip): 875 μA at ILOAD = 250 mA
  • Shutdown current:
    • 0.01 μA (typ) for legacy chip
    • 1.12 μA (typ) for new chip
  • Low noise: 30 μVRMS with 10-nF bypass capacitor
  • Output current limiting and thermal protection
  • Stable with 2.2-µF ceramic capacitors
  • High PSRR: 70 dB at 1 kHz, 40 dB at 1 MHz
  • Operating junction temperature: –40°C to 125°C
  • Package: 5-pin SOT-23 (DBV)