SNVS171J November   2001  – January 2017 LP2992


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sleep Mode
      2. 7.3.2 Low Ground Current
      3. 7.3.3 Low Noise
      4. 7.3.4 Enhanced Stability
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VOUT(TARGET) + 0.9 V ≥ VIN ≥ 16 V
      2. 7.4.2 Operation with ON/OFF Control
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. External Capacitors
          1. Input Capacitor
          2. Output Capacitor
          3. Noise Bypass Capacitor
        2. Capacitor Characteristics
          1. Tantalum
        3. Reverse Input-Output Voltage
        4. Power Dissipation
        5. Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 WSON Mounting
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The LP2992 is a 250-mA, fixed-output voltage regulator designed to provide ultralow-dropout and low noise in battery powered applications. The device is stable with output capacitor equivalent series resistance (ESR) as low as 5 mΩ which allows the use of ceramic capacitors on the output.

At 250-mA loading, the dropout voltage of the LP2992 is 850 mV maximum over temperature; thus, 1000-mV headroom is sufficient for operation over input and output voltage accuracy. The efficiency of the LP2992 in this configuration is VOUT/VIN = 76.7%. To achieve the smallest form factor, the SOT-23 package is selected.

Input and output capacitors are selected in accordance with Capacitor Characteristics. Ceramic capacitance of 1 µF for the input and that of 4.7 µF for the output are selected. With efficiency of 76.7% and a 250-mA load current, the internal power dissipation is 250 mW, which corresponds to 43.55°C junction temperature rise for the SOT-23 package. To minimize noise, a bypass capacitor (CBYPASS) of 0.01 µF is selected.

Typical Application

LP2992 20029402.png
*ON/OFF input must be actively terminated. Tie to the IN pin if this function is not to be used.
**Minimum capacitance is shown to ensure stability (may be increased without limit). Ceramic capacitor required for output (see Output Capacitor).
***Reduces output noise (may be omitted if application is not noise critical). Use ceramic or film type with very low leakage current (see Capacitor Characteristics).
Figure 34. Basic Application Circuit

Design Requirements

For basic design parameters, see Table 1.

Table 1. Design Parameters

Input voltage 4.3 V
Output voltage 3.3 V
Output current 150 mA (maximum)
1 mA (minimum)
Output capacitor range 4.7 µF

Detailed Design Procedure

External Capacitors

Like any low-dropout regulator, the LP2992 requires external capacitors for regulator stability. These capacitors must be correctly selected for good performance.

Input Capacitor

An input capacitor whose capacitance is ≥ 1 µF is required between the LP2992 input and ground (the amount of capacitance may be increased without limit).

This capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.


Tantalum capacitors can suffer catastrophic failure due to surge current when connected to a low-impedance source of power (like a battery or very large capacitor). If a tantalum capacitor is used at the input, it must be specified by the manufacturer to have a surge current rating sufficient for the application.

There are no requirements for ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance is ≥ 1 µF over the entire operating temperature range.

Output Capacitor

The LP2992 is designed specifically to work with ceramic output capacitors, using circuitry that allows the regulator to be stable across the entire range of output current with an output capacitor whose ESR is as low as 5 mΩ. It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics).

The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR value which is within the stable range. Curves are provided which show the stable ESR range as a function of load current (see Figure 35).

LP2992 20029407.png Figure 35. Stable ESR Range vs Load Current

The output capacitor must maintain its ESR within the stable region over the full operating temperature range of the application to assure stability.

The LP2992 requires a minimum of 4.7 µF on the output (output capacitor size can be increased without limit).

It is important to remember that capacitor tolerance and variation with temperature must be taken into consideration when selecting an output capacitor so that the minimum required amount of output capacitance is provided over the full operating temperature range. It must be noted that ceramic capacitors can exhibit large changes in capacitance with temperature (see Capacitor Characteristics).

The output capacitor must be located not more than 1 cm from the output pin and returned to a clean analog ground.

Noise Bypass Capacitor

Connecting a 10-nF capacitor to the BYPASS pin significantly reduces noise on the regulator output. It should be noted that the capacitor is connected directly to a high-impedance circuit in the bandgap reference.

Because this circuit has only a few microamperes flowing in it, any significant loading on this node causes a change in the regulated output voltage. For this reason, dc leakage current through the noise bypass capacitor must never exceed 100 nA, and must be kept as low as possible for best output voltage accuracy.

The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic capacitors with either NPO or COG dielectric typically have very low leakage. 10-nF polypropolene and polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low leakage current.

Capacitor Characteristics

The LP2992 was designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the 2.2-µF to 10-µF range, ceramics are the least expensive and also have the lowest ESR values (which makes them best for eliminating high-frequency noise). The ESR of a typical 4.7-µF ceramic capacitor is in the range of 5 mΩ to 10 mΩ, which easily meets the ESR limits required for stability by the LP2992.

One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Most large value ceramic capacitors (≥ 2.2 µF) are manufactured with the Z5U or Y5V temperature characteristic, which results in the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.

This could cause problems if a 4.7-µF capacitor were used on the output because it drops down to approximately 2.3 µF at high ambient temperatures (which could cause the LP2992 to oscillate). If Z5U or Y5V capacitors are used on the output, a minimum capacitance value of 10 µF must be observed.

A better choice for temperature coefficient in ceramic capacitors is X7R, which holds the capacitance within ±15%. Unfortunately, the larger values of capacitance are not offered by all manufacturers in the X7R dielectric.


Tantalum capacitors are less desirable than ceramics for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1-µF to 4.7-µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a Tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value.

It should also be noted that the ESR of a typical tantalum increases about 2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.

Reverse Input-Output Voltage

The PNP power transistor used as the pass element in the LP2992 has an inherent diode connected between the regulator output and input. During normal operation (where the input voltage is higher than the output) this diode is reverse-biased.

However, if the output is pulled above the input, this diode turns ON and current flows into the regulator output. In such cases, a parasitic SCR can latch which allows a high current to flow into VIN (and out the ground pin), which can damage the part.

In any application where the output may be pulled above the input, an external Schottky diode must be connected from VIN to VOUT (cathode on VIN, anode on VOUT), to limit the reverse voltage across the LP2992 to 0.3 V (see Absolute Maximum Ratings).

Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and load conditions and can be calculated with Equation 1.

Equation 1. PD(MAX) = (VIN(MAX) – VOUT) × IOUT

Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher voltage drops result in better dynamic (that is, PSRR and transient) performance.

On the WSON (NGD) package, the primary conduction path for heat is through the exposed power pad to the PCB. To ensure the device does not overheat, connect the exposed pad, through thermal vias, to an internal ground plane with an appropriate amount of copper PCB area.

On the SOT-23 (DBV) package, the primary conduction path for heat is through the pins to the PCB. The maximum allowable junction temperature (TJ(MAX))determines maximum power dissipation allowed (PD(MAX)) for the device package.

Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to Equation 2 or Equation 2:

Equation 2. TJ(MAX) = TA(MAX) + ( RθJA × PD(MAX))
Equation 3. PD = TJ(MAX) – TA(MAX) / RθJA

Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-spreading area, and is to be used only as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.

Estimating Junction Temperature

The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction temperatures of surface mount devices on a typical PCB board application. These characteristics are not true thermal resistance values, but rather package specific thermal characteristics that offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are used in accordance with Equation 4 or Equation 5.

Equation 4. TJ(MAX) = TTOP + (ΨJT × PD(MAX))


  • PD(MAX) is explained in Equation 3
  • TTOP is the temperature measured at the center-top of the device package.
Equation 5. TJ(MAX) = TBOARD + (ΨJB × PD(MAX))


  • PD(MAX) is explained in Equation 3.
  • TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the package edge.

For more information about the thermal characteristics ΨJT and ΨJB, see Semiconductor and IC Package Thermal Metrics; for more information about measuring TTOP and TBOARD, Using New Thermal Metrics (SBVA025); and for more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs. These application notes are available at

Application Curves

LP2992 20029433.png Figure 36. Load Transient Response
LP2992 20029435.png Figure 38. Line Transient Response
LP2992 20029439.png Figure 40. Turnon Time
LP2992 20029434.png Figure 37. Load Transient Response
LP2992 20029436.png Figure 39. Line Transient Response
LP2992 20029442.png Figure 41. Turnon Time