SNVS171J November   2001  – January 2017 LP2992


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sleep Mode
      2. 7.3.2 Low Ground Current
      3. 7.3.3 Low Noise
      4. 7.3.4 Enhanced Stability
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VOUT(TARGET) + 0.9 V ≥ VIN ≥ 16 V
      2. 7.4.2 Operation with ON/OFF Control
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. External Capacitors
          1. Input Capacitor
          2. Output Capacitor
          3. Noise Bypass Capacitor
        2. Capacitor Characteristics
          1. Tantalum
        3. Reverse Input-Output Voltage
        4. Power Dissipation
        5. Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 WSON Mounting
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


The LP2992 family of fixed-output, ultralow-dropout, and low-noise regulators offer exceptional and cost-effective performance for battery-powered applications. Available in output voltages from 1.5 V to 5 V, the family has an output tolerance of 1% for the A version and is capable of delivering 250-mA continuous load current. Using an optimized vertically integrated PNP (VIP) process, the LP2992 delivers unequaled performance. The dropout voltage and the GND pin current with 250 mA of load current are typically 450 mV and 1500 µA, respectively.

Functional Block Diagram

LP2992 20029401.png

Feature Description

Sleep Mode

When the ON/OFF pin is pulled low, the LP2992 enters a sleep mode, and less than 1-µA quiescent current is consumed. This function is designed for the application which needs a sleep mode to effectively enhance battery life cycle.

Low Ground Current

The LP2992 uses a vertical PNP process which allows for quiescent currents which are considerably lower than those associated with traditional lateral PNP regulators, typically 1500 µA at 250-mA load and 75 µA at 1-mA load.

Low Noise

The LP2992 includes a low-noise reference ensuring minimal noise during operation because the internal reference is normally the dominant term in a noise analysis. Further noise reduction can be achieved by adding an external bypass capacitor between the BYPASS pin and the GND pin. For more detailed information on noise reduction using the BYPASS pin, see Noise Bypass Capacitor.

Enhanced Stability

The LP2992 is designed specifically to work with ceramic output capacitors using circuitry that allows the regulator to be stable across the entire range of output current with an output capacitor whose ESR is as low as 5 mΩ. For output capacitor requirements, see Output Capacitor.

Overcurrent Protection

The internal current-limit circuit is used to protect the LDO against high-current faults or shorting events. The LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when the output impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output.

The LP2992 is featured with the foldback current limit that allows a high peak current when VOUT > 0.5 V, and then reduces the maximum output current as VOUT is forced to ground.

Overtemperature Protection

The LP2992 is designed with the thermal shutdown circuitry to turn off the output when excessive heat is dissipated in the LDO. The internal protection circuitry of the LP2992 is designed to protect against thermal overload conditions. Continuously running the device into thermal shutdown degrades its reliability.

Device Functional Modes

Operation with VOUT(TARGET) + 0.9 V ≥ VIN ≥ 16 V

The LP2992 operates if the input voltage is equal to or exceeds VOUT(TARGET) + 0.9 V. At input voltages below the minimum VIN requirement, the device does not operate correctly and output voltage may not reach a target value.

Operation with ON/OFF Control

If the voltage on the ON/OFF pin is less than 0.15 V, the device is disabled and, in this shutdown state, current does not exceed 2 µA. Raising the voltage at the ON/OFF pin above 1.6 V initiates the start-up sequence of the device. If this feature is not to be used, the ON/OFF input must be tied to VIN to keep the regulator output on at all times.

To assure proper operation, the signal source used to drive the ON/OFF input must be able to swing above and below the specified turnon/turnoff voltage thresholds listed in the Electrical Characteristics section under VON/OFF. To prevent mis-operation, the turnon (and turnoff) voltage signals applied to the ON/OFF input must have a slew rate which is ≥ 40 mV/µs.


The regulator output voltage can not be ensured if a slow-moving AC (or DC) signal is applied that is in the range between the specified turnon and turnoff voltages listed under the electrical specification VON/OFF (see Electrical Characteristics).