SNVS171J November   2001  – January 2017 LP2992


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sleep Mode
      2. 7.3.2 Low Ground Current
      3. 7.3.3 Low Noise
      4. 7.3.4 Enhanced Stability
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VOUT(TARGET) + 0.9 V ≥ VIN ≥ 16 V
      2. 7.4.2 Operation with ON/OFF Control
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. External Capacitors
          1. Input Capacitor
          2. Output Capacitor
          3. Noise Bypass Capacitor
        2. Capacitor Characteristics
          1. Tantalum
        3. Reverse Input-Output Voltage
        4. Power Dissipation
        5. Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 WSON Mounting
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability.

TI also recommends a ground reference plane either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements.

Layout Examples

LP2992 SOT23_layout_snvs171.gif Figure 42. LP2992 SOT-23 Package Typical Layout
LP2992 WSON_layout_snvs171.gif Figure 43. LP2992 WSON Package Typical Layout

WSON Mounting

The WSON package requires specific mounting techniques which are detailed in AN-1187 Leadless Leadframe Package (LLP). Referring to the section PCB Design Recommendations, note that the pad style which must be used with the WSON package is the NSMD (non-solder mask defined) type.

The thermal dissipation of the WSON package is directly related to the printed circuit board construction and the amount of additional copper area.