SNVS174I February   2003  – February 2015 LP3852 , LP3855

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematics
  5. 5 Revision History
  6. 6 Voltage Options
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 SENSE Pin
      2. 9.3.2 SHUTDOWN (SD) Operation
      3. 9.3.3 Dropout Voltage
      4. 9.3.4 Reverse Current Path
      5. 9.3.5 Short-Circuit Protection
      6. 9.3.6 ERROR Flag Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation with VOUT(TARGET) + 0.1 V ≤ VIN ≤ 7 V
      2. 9.4.2 Operation With SD Pin Control
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 External Capacitors
          1. 10.2.2.1.1 Input Capacitor
          2. 10.2.2.1.2 Output Capacitor
        2. 10.2.2.2 Operation with Ceramic Output Capacitors
        3. 10.2.2.3 Selecting A Capacitor
        4. 10.2.2.4 Capacitor Characteristics
          1. 10.2.2.4.1 Ceramic
          2. 10.2.2.4.2 Tantalum
          3. 10.2.2.4.3 Aluminum
        5. 10.2.2.5 Turnon Characteristics For Output Voltages Programmed to 2 V or Below
        6. 10.2.2.6 Output Noise
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 RFI and/or EMI Susceptibility
    4. 12.4 Power Dissipation/Heatsinking
      1. 12.4.1 Heatsinking TO-220 Package
      2. 12.4.2 Heatsinking TO-263 Package
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Lead temperature (soldering, 5 sec.) 260 °C
Power dissipation(2) Internally limited
Input supply voltage (survival) –0.3 7.5 V
Shutdown input voltage (survival) –0.3 7.5
Output voltage (survival)(3), (4) –0.3 6
IOUT (survival) Short-circuit protected
Maximum voltage for ERROR pin VIN
Maximum voltage for SENSE pin VOUT
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be derated at RθJA = 32°C/W (with 0.5 in2, 1-oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO-263 surface-mount package must be derated at RθJA = 40.3°C/W (with 0.5 in2, 1-oz. copper area), junction-to-ambient. See Application and Implementation section.
(3) If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.
(4) The output PMOS structure contains a diode between the IN and OUT terminals. This diode is normally reverse biased. This diode will get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200 mA of DC current and 1 A of peak current.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input supply voltage(1) 2.5 7 V
Shutdown input voltage −0.3 7
Maximum operating current (DC) 1.5 A
Junction temperature −40 125 °C
(1) The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5 V, whichever is greater.

8.4 Thermal Information

THERMAL METRIC(1) LP3852/LP3855 UNIT
NDC KTT NDH
5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance, High-K 65.2 40.3 32 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 47.2 43.4 43.8
RθJB Junction-to-board thermal resistance 9.9 23.1 18.6
ψJT Junction-to-top characterization parameter 3.4 11.5 8.8
ψJB Junction-to-board characterization parameter 9.7 22 18
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 1 1.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

Unless otherwise specified: VIN = VOUT(NOM) + 1 V, IOUT = 10 mA, COUT = 10 µF, VSD = 2 V, TJ = 25°C.
PARAMETER TEST CONDITIONS MIN(2) TYP(1) MAX(2) UNIT
VOUT Output voltage tolerance(3) VOUT +1 V ≤ VIN ≤ 7 V
10 mA ≤ IOUT ≤ 1.5 A		 –1.5% 0 1.5%
For –40°C ≤ TJ ≤ 125°C –3% 3%
ΔVOUT/ΔVIN Output voltage line regulation(3) VOUT +1 V ≤ VIN ≤ 7 V 0.02%
For –40°C ≤ TJ ≤ 125°C 0.06%
ΔVOUT/ΔIOUT Output voltage load regulation(3) 10 mA ≤ IOUT ≤ 1.5 A 0.06%
For –40°C ≤ TJ ≤ 125°C 0.12%
VIN - VOUT Dropout voltage
TO-263 and TO-220(4)		 IOUT = 150 mA 24 35 mV
For –40°C ≤ TJ ≤ 125°C 45
IOUT = 1.5A 240 280
For –40°C ≤ TJ ≤ 125°C 380
Dropout voltage
SOT(4), (5)		 IOUT = 150mA 26 35
For –40°C ≤ TJ ≤ 125°C 45
IOUT = 1.5 A 260 320
For –40°C ≤ TJ ≤ 125°C 435
IGND Ground pin current in normal operation mode IOUT = 150 mA 3 9 mA
For –40°C ≤ TJ ≤ 125°C 10
IOUT = 1.5 A 3 9
For –40°C ≤ TJ ≤ 125°C 10
IGND Ground pin current in shutdown mode VSD ≤ 0.3V 0.01 10 µA
-40°C ≤ TJ ≤ 85°C 50
IOUT(PK) Peak output current VO ≥ VO(NOM) – 4% 1.8 A
SHORT CIRCUIT PROTECTION
ISC Short circuit current 3.2 A
SHUTDOWN INPUT
VSDT Shutdown threshold VSDT Rising from 0.3 V until
Output = ON		 1.3 V
For –40°C ≤ TJ ≤ 125°C 2
VSDT Falling from 2 V until
Output = OFF		 1.3
For –40°C ≤ TJ ≤ 125°C 0.3
TdOFF Turnoff delay IOUT = 1.5 A 20 µs
TdON Turnon delay IOUT = 1.5 A 25 µs
ISD SD input current VSD = VIN 1 nA
ERROR PIN
VT Threshold See(6) 10%
For –40°C ≤ TJ ≤ 125°C 5% 16%
VTH Threshold hysteresis See(6) 5%
For –40°C ≤ TJ ≤ 125°C 2% 8%
VEF(Sat) ERROR pin saturation Isink = 100 µA 0.02 V
For –40°C ≤ TJ ≤ 125°C 0.1
Td Flag reset delay 1 µs
Ilk ERROR pin leakage current 1 nA
Imax ERROR pin sink current VError = 0.5 V 1 mA
AC PARAMETERS
PSRR Ripple rejection VIN = VOUT + 1 V
COUT = 10 µF
VOUT = 3.3V, f = 120 Hz		 73 dB
VIN = VOUT + 0.5 V
COUT = 10 µF
VOUT = 3.3V, f = 120 Hz		 57
ρn(l/f) Output noise density f = 120 Hz 0.8 µV
en Output noise voltage BW = 10Hz – 100 kHz
VOUT = 2.5 V		 150 µV (rms)
BW = 300 Hz – 300 kHz
VOUT = 2.5 V		 100
(1) Typical numbers are at 25°C and represent the most likely parametric norm.
(2) Limits are specified by testing, design, or statistical correlation.
(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification.
(4) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5 V, the drop-out voltage is nothing but the input to output differential, since the minimum input voltage is 2.5 V.
(5) The SOT-223 package devices have slightly higher dropout due to increased bond wire resistance.
(6) ERROR threshold and hysteresis are specified as percentage of regulated output voltage. See ERROR Flag Operation.

8.6 Typical Characteristics

Unless otherwise specified: TJ = 25°C, COUT = 10 µF, CIN = 10 µF, SD pin is tied to VIN, VOUT = 2.5 V, VIN = VOUT(NOM) + 1 V, IOUT = 10 mA.
LP3852 LP3855 20031062.gif
Figure 1. Dropout Voltage vs Output Load Current
LP3852 LP3855 20031055.gif
Figure 3. SD IQ vs Junction Temperature
LP3852 LP3855 20031058.gif
Figure 5. DC Load Reg. vs Junction Temperature
LP3852 LP3855 20031060.gif
Figure 7. VIN vs VOUT Over Temperature
LP3852 LP3855 20031082.gif
CIN = COUT = 100 µF, OSCON
Figure 9. Load Transient Response
LP3852 LP3855 20031085.gif
CIN = COUT = 100 µF, Tantalum
Figure 11. Load Transient Response
LP3852 LP3855 20031094.gif
CIN = 2 X 10 µF Ceramic
COUT = 2 X 10µF Ceramic
Figure 13. Load Transient Response
LP3852 LP3855 20031054.gif
IOUT = 1.5 A
Figure 2. Ground Current vs Output Voltage
LP3852 LP3855 20031057.gif
Figure 4. ERROR Threshold vs Junction Temperature
LP3852 LP3855 20031059.gif
Figure 6. DC Line Regulation vs Temperature
LP3852 LP3855 20031061.gif
Figure 8. Noise vs Frequency
LP3852 LP3855 20031083.gif
CIN = COUT = 100 µF, POSCAP
Figure 10. Load Transient Response
LP3852 LP3855 20031093.gif
CIN = 2 X 10 µF Ceramic
COUT = 2 X 10µF Ceramic
Figure 12. Load Transient Response