SNVSBK2 September   2019 LP8733

PRODUCTION DATA.  

  1. Features
    1.     Simplified Schematic
  2. Applications
  3. Description
    1.     DC/DC Efficiency vs Output Current
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Dual-Phase Operation and Phase-Adding/Shedding
        3. 7.3.1.3 Transition Between PWM and PFM Modes
        4. 7.3.1.4 Dual-Phase Switcher Configurations
        5. 7.3.1.5 Buck Converter Load Current Measurement
        6. 7.3.1.6 Spread-Spectrum Mode
      2. 7.3.2  Sync Clock Functionality
      3. 7.3.3  Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4  Power-Up
      5. 7.3.5  Regulator Control
        1. 7.3.5.1 Enabling and Disabling Regulators
        2. 7.3.5.2 Changing Output Voltage
      6. 7.3.6  Enable and Disable Sequences
      7. 7.3.7  Device Reset Scenarios
      8. 7.3.8  Diagnosis and Protection Features
        1. 7.3.8.1 Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1 PGOOD Pin Gated Mode
          2. 7.3.8.1.2 PGOOD Pin Continuous Mode
        2. 7.3.8.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1 Output Power Limit
          2. 7.3.8.2.2 Thermal Warning
        3. 7.3.8.3 Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2 Overvoltage Protection
          3. 7.3.8.3.3 Thermal Shutdown
        4. 7.3.8.4 Fault (Power Down)
          1. 7.3.8.4.1 Undervoltage Lockout
      9. 7.3.9  Operation of the GPO Signals
      10. 7.3.10 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
          1. Table 8. DEV_REV Register Field Descriptions
        2. 7.6.1.2  OTP_REV
          1. Table 9. OTP_REV Register Field Descriptions
        3. 7.6.1.3  BUCK0_CTRL_1
          1. Table 10. BUCK0_CTRL_1 Register Field Descriptions
        4. 7.6.1.4  BUCK0_CTRL_2
          1. Table 11. BUCK0_CTRL_2 Register Field Descriptions
        5. 7.6.1.5  BUCK1_CTRL_1
          1. Table 12. BUCK1_CTRL_1 Register Field Descriptions
        6. 7.6.1.6  BUCK1_CTRL_2
          1. Table 13. BUCK1_CTRL_2 Register Field Descriptions
        7. 7.6.1.7  BUCK0_VOUT
          1. Table 14. BUCK0_VOUT Register Field Descriptions
        8. 7.6.1.8  BUCK1_VOUT
          1. Table 15. BUCK1_VOUT Register Field Descriptions
        9. 7.6.1.9  LDO0_CTRL
          1. Table 16. LDO0_CTRL Register Field Descriptions
        10. 7.6.1.10 LDO1_CTRL
          1. Table 17. LDO1_CTRL Register Field Descriptions
        11. 7.6.1.11 LDO0_VOUT
          1. Table 18. LDO0_VOUT Register Field Descriptions
        12. 7.6.1.12 LDO1_VOUT
          1. Table 19. LDO1_VOUT Register Field Descriptions
        13. 7.6.1.13 BUCK0_DELAY
          1. Table 20. BUCK0_DELAY Register Field Descriptions
        14. 7.6.1.14 BUCK1_DELAY
          1. Table 21. BUCK1_DELAY Register Field Descriptions
        15. 7.6.1.15 LDO0_DELAY
          1. Table 22. LDO0_DELAY Register Field Descriptions
        16. 7.6.1.16 LDO1_DELAY
          1. Table 23. LDO1_DELAY Register Field Descriptions
        17. 7.6.1.17 GPO_DELAY
          1. Table 24. GPO_DELAY Register Field Descriptions
        18. 7.6.1.18 GPO2_DELAY
          1. Table 25. GPO2_DELAY Register Field Descriptions
        19. 7.6.1.19 GPO_CTRL
          1. Table 26. GPO_CTRL Register Field Descriptions
        20. 7.6.1.20 CONFIG
          1. Table 27. CONFIG Register Field Descriptions
        21. 7.6.1.21 PLL_CTRL
          1. Table 28. PLL_CTRL Register Field Descriptions
        22. 7.6.1.22 PGOOD_CTRL_1
          1. Table 29. PGOOD_CTRL_1 Register Field Descriptions
        23. 7.6.1.23 PGOOD_CTRL_2
          1. Table 30. PGOOD_CTRL_2 Register Field Descriptions
        24. 7.6.1.24 PG_FAULT
          1. Table 31. PG_FAULT Register Field Descriptions
        25. 7.6.1.25 RESET
          1. Table 32. RESET Register Field Descriptions
        26. 7.6.1.26 INT_TOP_1
          1. Table 33. INT_TOP_1 Register Field Descriptions
        27. 7.6.1.27 INT_TOP_2
          1. Table 34. INT_TOP_2 Register Field Descriptions
        28. 7.6.1.28 INT_BUCK
          1. Table 35. INT_BUCK Register Field Descriptions
        29. 7.6.1.29 INT_LDO
          1. Table 36. INT_LDO Register Field Descriptions
        30. 7.6.1.30 TOP_STAT
          1. Table 37. TOP_STAT Register Field Descriptions
        31. 7.6.1.31 BUCK_STAT
          1. Table 38. BUCK_STAT Register Field Descriptions
        32. 7.6.1.32 LDO_STAT
          1. Table 39. LDO_STAT Register Field Descriptions
        33. 7.6.1.33 TOP_MASK_1
          1. Table 40. TOP_MASK_1 Register Field Descriptions
        34. 7.6.1.34 TOP_MASK_2
          1. Table 41. TOP_MASK_2 Register Field Descriptions
        35. 7.6.1.35 BUCK_MASK
          1. Table 42. BUCK_MASK Register Field Descriptions
        36. 7.6.1.36 LDO_MASK
          1. Table 43. LDO_MASK Register Field Descriptions
        37. 7.6.1.37 SEL_I_LOAD
          1. Table 44. SEL_I_LOAD Register Field Descriptions
        38. 7.6.1.38 I_LOAD_2
          1. Table 45. I_LOAD_2 Register Field Descriptions
        39. 7.6.1.39 I_LOAD_1
          1. Table 46. I_LOAD_1 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Input Capacitor Selection
        5. 8.2.1.5 LDO Output Capacitor Selection
        6. 8.2.1.6 Current Limit vs. Maximum Output Current
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application Curves

Measurements are done using typical application set up with connections shown in Typical Applications. Graphs may not reflect the OTP default settings. Unless otherwise specified: V(VIN_Bx) = V(VIN_LDOx) = V(VANA) = 3.7 V, VOUT_Bx = 1 V, VOUT_LDOx = 1 V, TA = 25°C, L = 0.47 µH (TOKO DFE252012PD-R47M), COUT_BUCK = 22 µF / phase, and CPOL_BUCK = 22 µF, COUT_LDO = 1 µF.

LP8733 D003_SNVSAB5.gif
VOUT = 1.8 V
Figure 71. Buck Efficiency in PFM/PWM and Forced PWM Mode (Single-Phase Output)
LP8733 D007_SNVSAB5.gif
VIN = 3.3 V
Figure 73. Buck Efficiency in Forced PWM Mode (Single-Phase Output)
LP8733 D011_SNVSAB5.gif
VIN = 5 V
Figure 75. Buck Efficiency in Forced PWM Mode (Single-Phase Output)
LP8733 D015_SNVSAB5.gif
VOUT = 1 V
Figure 77. Buck Output Voltage vs Load Current in Forced PWM Mode (Single-Phase Output)
LP8733 D019_SNVSAB5.gif
VOUT = 1 V
Figure 79. Buck Output Voltage vs Load Current in PFM/PWM Mode (Single-Phase Output)
LP8733 D021_SNVSAB5.gif
VOUT = 1 V Load = 1 A
Figure 81. Buck Output Voltage vs Input Voltage in PWM Mode (Single-Phase Output)
LP8733 D023_SNVSAB5.gif
Load = 1 A (PWM) and 0.1 A (PFM)
Figure 83. Buck Output Voltage vs Temperature
LP8733 SNVSAB5_D026.png
Slew-rate = 10 mV/µs ILOAD = 0 A VOUT = 1 V
Figure 85. Buck Start-Up With EN1, Forced PWM Mode (Single-Phase Output)
LP8733 SNVSAB5_D028.png
Slew-rate = 10 mV/µs RLOAD = 1 Ω VOUT = 1 V
Figure 87. Buck Start-Up with EN1, Forced PWM Mode (Single-Phase Output)
LP8733 SNVSAB5_D030.png
Slew-rate = 10 mV/µs RLOAD = 1 Ω VOUT = 1 V
Figure 89. Buck Shutdown With EN1, Forced PWM Mode (Single-Phase Output)
LP8733 SNVSAB5_D032.png
IOUT = 10 mA
Figure 91. Buck Output Voltage Ripple, PFM Mode (Single-Phase Output)
LP8733 SNVSAB5_D034.png
IOUT = 200 mA
Figure 93. Buck Output Voltage Ripple,
Forced PWM Mode (Single-Phase Output)
LP8733 SNVSAB5_D036.png
Figure 95. Buck Transient From PFM-to-PWM Mode (Single-Phase Output)
LP8733 SNVSAB5_D038.png
Figure 97. Buck Transient From PWM-to-PFM Mode (Single-Phase Output)
LP8733 SNVSAB5_D040.png
Figure 99. Buck Transient From 1-Phase to 2-Phase Operation (Dual-Phase Output)
LP8733 SNVSAB5_D042.png
IOUT = 0.1 A → 2 A → 0.1 A TR = TF = 400 ns
Figure 101. Buck Transient Load Step Response, AUTO Mode (Single-Phase Output)
LP8733 SNVSAB5_D044.png
IOUT = 0.1 A → 2 A → 0.1 A TR = TF = 400 ns
Figure 103. Buck Transient Load Step Response, Forced PWM Mode (Single-Phase Output)
LP8733 SNVSAB5_D046.gif
Figure 105. Buck VOUT Transition from 0.6 V to 1.4 V With Different Slew Rate Settings
LP8733 SNVSAB5_D048.png
Figure 107. Buck Start-Up With Short on Output (Single-Phase Output)
LP8733 D050_SNVSAB5.gif
VOUT = 1 V
Figure 109. LDO Output Voltage vs Load Current
LP8733 D052_SNVSAB5.gif
VOUT = 1 V Load = 200 mA
Figure 111. LDO Output Voltage vs Temperature
LP8733 SNVSAB5_D054.png
RLOAD = 3.3 Ω VOUT = 1 V
Figure 113. LDO Start-Up
LP8733 SNVSAB5_D056.png
IOUT = 0 A → 0.3 A → 0 A TR = TF = 1 µs
Figure 115. LDO Transient Load Step Response
LP8733 SNVSAB5_D058.png
Figure 117. LDO VOUT Transition from 1.2 V to 1.8 V
LP8733 D005_SNVSAB5.gif
VOUT = 1.8 V
Figure 72. Buck Efficiency in PFM/PWM and Forced PWM Mode (Dual-Phase Output)
LP8733 D009_SNVSAB5.gif
VIN = 3.3 V
Figure 74. Buck Efficiency in Forced PWM Mode (Dual-Phase Output)
LP8733 D013_SNVSAB5.gif
VIN = 5 V
Figure 76. Buck Efficiency in Forced PWM Mode (Dual-Phase Output)
LP8733 D017_SNVSAB5.gif
VOUT = 1 V
Figure 78. Buck Output Voltage vs Load Current in Forced PWM Mode (Dual-Phase Output)
LP8733 D020_SNVSAB5.gif
VOUT = 1 V
Figure 80. Buck Output Voltage vs Load Current in PFM/PWM Mode (Dual-Phase Output)
LP8733 D022_SNVSAB5.gif
VOUT = 1 V Load = 1 A
Figure 82. Buck Output Voltage vs Input Voltage in PWM Mode (Dual-Phase Output)
LP8733 D025_SNVSAB5.gif
VIN = 3.7 V
Figure 84. Buck Phase Adding and Shedding vs Load Current (Dual-Phase Output)
LP8733 SNVSAB5_D027.png
Slew-rate = 10 mV/µs ILOAD = 0 A VOUT = 1 V
Figure 86. Buck Start-Up With EN1, Forced PWM Mode (Dual-Phase Output)
LP8733 SNVSAB5_D029.png
Slew-rate = 10 mV/µs RLOAD = 0.5 Ω VOUT = 1 V
Figure 88. Buck Start-Up with EN1, Forced PWM Mode (Dual-Phase Output)
LP8733 SNVSAB5_D031.png
Slew-rate = 10 mV/µs RLOAD = 0.5 Ω VOUT = 1 V
Figure 90. Buck Shutdown With EN1, Forced PWM Mode (Dual-Phase Output)
LP8733 SNVSAB5_D033.png
IOUT = 10 mA
Figure 92. Buck Output Voltage Ripple, PFM Mode (Dual-Phase Output)
LP8733 SNVSAB5_D035.png
IOUT = 200 mA
Figure 94. Buck Output Voltage Ripple,
Forced PWM Mode (Dual-Phase Output)
LP8733 SNVSAB5_D037.png
Figure 96. Buck Transient From PFM-to-PWM Mode (Dual-Phase Output)
LP8733 SNVSAB5_D039.png
Figure 98. Buck Transient From PWM-to-PFM Mode (Dual-Phase Output)
LP8733 SNVSAB5_D041.png
Figure 100. Buck Transient From 2-Phase to 1-Phase Operation (Dual-Phase Output)
LP8733 SNVSAB5_D043.png
IOUT = 0.1 A → 4 A → 0.1 A TR = TF = 400 ns
Figure 102. Buck Transient Load Step Response, AUTO Mode (Dual-Phase Output)
LP8733 SNVSAB5_D045.png
IOUT = 0.1 A → 4 A → 0.1 A TR = TF = 400 ns
Figure 104. Buck Transient Load Step Response, Forced PWM Mode (Dual-Phase Output)
LP8733 SNVSAB5_D047.gif
Figure 106. Buck VOUT Transition from 1.4 V to 0.6 V With Different Slew Rate Settings
LP8733 SNVSAB5_D049.png
Figure 108. Buck Start-up With Short on Output (Dual-Phase Output)
LP8733 D051_SNVSAB5.gif
VOUT = 1 V Load = 200 mA
Figure 110. LDO Output Voltage vs Input Voltage
LP8733 SNVSAB5_D053.png
ILOAD = 0 A VOUT = 1 V
Figure 112. LDO Start-Up
LP8733 SNVSAB5_D055.png
ILOAD = 0 A VOUT = 1 V
Figure 114. LDO Shutdown
LP8733 SNVSAB5_D057.png
Figure 116. LDO VOUT Transition from 1.8 V to 1.2 V
LP8733 SNVSAB5_D059.png
Start-up delay is 500 µs
Figure 118. LDO Start-Up With Short on Output