SNVSBK2 September 2019 LP8733
The output voltage of the regulator can be changed by writing to the BUCKx_VOUT and LDOx_VOUT register. The voltage change for the buck regulator is always slew-rate controlled, and the slew-rate is defined by the BUCKx_SLEW_RATE[2:0] bits in the BUCKx_CTRL_2 register. During voltage change, the forced PWM mode is used automatically. If the dual-phase operation is forced by the BUCK0_FPWM_MP bit in the BUCK0_CTRL_1 register, the regulator operates in dual-phase mode. If the dual-phase operation is not forced, the number of phases are added and shedded automatically to follow the required slew rate. When the programmed output voltage is achieved, the mode becomes the one defined by the load current, the BUCKx_FPWM bit in the BUCKx_CTRL_1 register, and the BUCK0_FPWM_MP bit.
The voltage change and Power-Good interrupts are shown in Figure 15.
During an LDO voltage change, the internal reference for the Power-Good detection is also changed. For this reason when the output voltage is changing, toggling of the Power-Good signal may still indicate a valid output. This period takes less than 100 µs and after that time the Power Good gives correct value.