SNVSBK2 September   2019 LP8733

PRODUCTION DATA.  

  1. Features
    1.     Simplified Schematic
  2. Applications
  3. Description
    1.     DC/DC Efficiency vs Output Current
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Dual-Phase Operation and Phase-Adding/Shedding
        3. 7.3.1.3 Transition Between PWM and PFM Modes
        4. 7.3.1.4 Dual-Phase Switcher Configurations
        5. 7.3.1.5 Buck Converter Load Current Measurement
        6. 7.3.1.6 Spread-Spectrum Mode
      2. 7.3.2  Sync Clock Functionality
      3. 7.3.3  Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4  Power-Up
      5. 7.3.5  Regulator Control
        1. 7.3.5.1 Enabling and Disabling Regulators
        2. 7.3.5.2 Changing Output Voltage
      6. 7.3.6  Enable and Disable Sequences
      7. 7.3.7  Device Reset Scenarios
      8. 7.3.8  Diagnosis and Protection Features
        1. 7.3.8.1 Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1 PGOOD Pin Gated Mode
          2. 7.3.8.1.2 PGOOD Pin Continuous Mode
        2. 7.3.8.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1 Output Power Limit
          2. 7.3.8.2.2 Thermal Warning
        3. 7.3.8.3 Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2 Overvoltage Protection
          3. 7.3.8.3.3 Thermal Shutdown
        4. 7.3.8.4 Fault (Power Down)
          1. 7.3.8.4.1 Undervoltage Lockout
      9. 7.3.9  Operation of the GPO Signals
      10. 7.3.10 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
          1. Table 8. DEV_REV Register Field Descriptions
        2. 7.6.1.2  OTP_REV
          1. Table 9. OTP_REV Register Field Descriptions
        3. 7.6.1.3  BUCK0_CTRL_1
          1. Table 10. BUCK0_CTRL_1 Register Field Descriptions
        4. 7.6.1.4  BUCK0_CTRL_2
          1. Table 11. BUCK0_CTRL_2 Register Field Descriptions
        5. 7.6.1.5  BUCK1_CTRL_1
          1. Table 12. BUCK1_CTRL_1 Register Field Descriptions
        6. 7.6.1.6  BUCK1_CTRL_2
          1. Table 13. BUCK1_CTRL_2 Register Field Descriptions
        7. 7.6.1.7  BUCK0_VOUT
          1. Table 14. BUCK0_VOUT Register Field Descriptions
        8. 7.6.1.8  BUCK1_VOUT
          1. Table 15. BUCK1_VOUT Register Field Descriptions
        9. 7.6.1.9  LDO0_CTRL
          1. Table 16. LDO0_CTRL Register Field Descriptions
        10. 7.6.1.10 LDO1_CTRL
          1. Table 17. LDO1_CTRL Register Field Descriptions
        11. 7.6.1.11 LDO0_VOUT
          1. Table 18. LDO0_VOUT Register Field Descriptions
        12. 7.6.1.12 LDO1_VOUT
          1. Table 19. LDO1_VOUT Register Field Descriptions
        13. 7.6.1.13 BUCK0_DELAY
          1. Table 20. BUCK0_DELAY Register Field Descriptions
        14. 7.6.1.14 BUCK1_DELAY
          1. Table 21. BUCK1_DELAY Register Field Descriptions
        15. 7.6.1.15 LDO0_DELAY
          1. Table 22. LDO0_DELAY Register Field Descriptions
        16. 7.6.1.16 LDO1_DELAY
          1. Table 23. LDO1_DELAY Register Field Descriptions
        17. 7.6.1.17 GPO_DELAY
          1. Table 24. GPO_DELAY Register Field Descriptions
        18. 7.6.1.18 GPO2_DELAY
          1. Table 25. GPO2_DELAY Register Field Descriptions
        19. 7.6.1.19 GPO_CTRL
          1. Table 26. GPO_CTRL Register Field Descriptions
        20. 7.6.1.20 CONFIG
          1. Table 27. CONFIG Register Field Descriptions
        21. 7.6.1.21 PLL_CTRL
          1. Table 28. PLL_CTRL Register Field Descriptions
        22. 7.6.1.22 PGOOD_CTRL_1
          1. Table 29. PGOOD_CTRL_1 Register Field Descriptions
        23. 7.6.1.23 PGOOD_CTRL_2
          1. Table 30. PGOOD_CTRL_2 Register Field Descriptions
        24. 7.6.1.24 PG_FAULT
          1. Table 31. PG_FAULT Register Field Descriptions
        25. 7.6.1.25 RESET
          1. Table 32. RESET Register Field Descriptions
        26. 7.6.1.26 INT_TOP_1
          1. Table 33. INT_TOP_1 Register Field Descriptions
        27. 7.6.1.27 INT_TOP_2
          1. Table 34. INT_TOP_2 Register Field Descriptions
        28. 7.6.1.28 INT_BUCK
          1. Table 35. INT_BUCK Register Field Descriptions
        29. 7.6.1.29 INT_LDO
          1. Table 36. INT_LDO Register Field Descriptions
        30. 7.6.1.30 TOP_STAT
          1. Table 37. TOP_STAT Register Field Descriptions
        31. 7.6.1.31 BUCK_STAT
          1. Table 38. BUCK_STAT Register Field Descriptions
        32. 7.6.1.32 LDO_STAT
          1. Table 39. LDO_STAT Register Field Descriptions
        33. 7.6.1.33 TOP_MASK_1
          1. Table 40. TOP_MASK_1 Register Field Descriptions
        34. 7.6.1.34 TOP_MASK_2
          1. Table 41. TOP_MASK_2 Register Field Descriptions
        35. 7.6.1.35 BUCK_MASK
          1. Table 42. BUCK_MASK Register Field Descriptions
        36. 7.6.1.36 LDO_MASK
          1. Table 43. LDO_MASK Register Field Descriptions
        37. 7.6.1.37 SEL_I_LOAD
          1. Table 44. SEL_I_LOAD Register Field Descriptions
        38. 7.6.1.38 I_LOAD_2
          1. Table 45. I_LOAD_2 Register Field Descriptions
        39. 7.6.1.39 I_LOAD_1
          1. Table 46. I_LOAD_1 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Input Capacitor Selection
        5. 8.2.1.5 LDO Output Capacitor Selection
        6. 8.2.1.6 Current Limit vs. Maximum Output Current
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V, unless otherwise noted.(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL COMPONENTS
CIN_BUCK Input filtering capacitance for buck regulators Effective capacitance, connected from VIN_Bx to PGND_Bx 1.9 10 µF
COUT_BUCK Output filtering capacitance for buck regulators Effective capacitance per phase 10 22 500 µF
CPOL_BUCK Point-of-load (POL) capacitance for buck regulators Optional POL capacitance 22 µF
COUT-TOTAL_BUCK Buck output capacitance, total (local and POL) Total output capacitance per phase 500 µF
CIN_LDO Input filtering capacitance for LDO regulators Effective capacitance, connected from VIN_LDOx to AGND. CIN_LDO must be at least two times larger than COUT_LDO 0.6 2.2 µF
COUT_LDO Output filtering capacitance for LDO regulators Effective capacitance 0.4 1 2.7 µF
ESRC Input and output capacitor ESR [1-10] MHz 2 10
L Inductor Inductance of the inductor 0.47 µH
–30% 30%
DCRL Inductor DCR 25
BUCK REGULATORS
V(VIN_Bx), V(VANA) Input voltage range VIN_Bx and VANA pins must be connected to the same supply line 2.8 3.7 5.5 V
VOUT_Bx Output voltage Programmable voltage range 0.7 1 3.36 V
Step size, 0.7 V ≤ VOUT < 0.73 V 10 mV
Step size, 0.73 V ≤ VOUT < 1.4 V 5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V 20
IOUT_Bx Output current Output current, single-phase output 3(3) A
Output current, dual-phase output 6(3)
Input and Output voltage difference Minimum voltage between V(VIN_Bx) and VOUT to fulfill the electrical characteristics 0.8 V
VOUT_Bx_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature Force PWM mode, VOUT < 1 V –20 20 mV
Force PWM mode, VOUT ≥ 1 V –2% 2%
PFM mode, VOUT < 1 V, the average output voltage level is increased by max. 20 mV –20 40 mV
PFM mode, VOUT ≥ 1 V, the average output voltage level is increased by max. 20 mV –2% 2% + 20 mV
Ripple voltage, single-phase output PWM mode 10 mVp-p
PFM mode, IOUT = 10 mA 25
Ripple voltage, dual-phase output PWM mode 5 mVp-p
PFM mode, IOUT = 10 mA 4
DCLNR DC line regulation IOUT = 1 A ±0.05 %/V
DCLDR DC load regulation in PWM mode VOUT_Bx = 1 V, IOUT from 0 to IOUT(max) 0.3%
TLDSR Transient load step response, single-phase output IOUT = 0.1 A to 2 A, TR = TF = 400 ns, PWM mode ±55 mV
Transient load step response, dual-phase output IOUT = 0.1 A to 4 A, TR = TF = 400 ns, PWM mode ±50 mV
TLNSR Transient line response V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) ±10 mV
ILIM FWD Forward current limit per phase (peak for every switching cycle) Programmable range 1.5 4 A
Step size 0.5
Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 4 A –5% 7.5% 20%
Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A –20% 7.5% 20%
ILIM NEG Negative current limit per phase 1.6 2.0 3.0 A
RDS(ON) HS FET On-resistance, high-side FET Each phase, between VIN_Bx and SW_Bx pins (I = 1 A) 50 110
RDS(ON) LS FET On-resistance, low-side FET Each phase, between SW_Bx and PGND_Bx pins (I = 1 A) 45 90
ƒSW Switching frequency PWM mode 1.8 2 2.2 MHz
Current balancing for dual-phase output Current mismatch between phases, IOUT > 1 mA 10%
Start-up time (soft start) From ENx to VOUT_Bx = 0.35 V (slew-rate control begins) 120 µs
Output voltage slew-rate(4) SLEW_RATEx[2:0] = 010, COUT-TOTAL_BUCK < 80 µF per phase –15% 10 15% mV/µs
SLEW_RATEx[2:0] = 011, COUT-TOTAL_BUCK < 130 µF per phase 7.5
SLEW_RATEx[2:0] = 100, COUT-TOTAL_BUCK < 250 µF per phase 3.8
SLEW_RATEx[2:0] = 101, COUT-TOTAL_BUCK < 500 µF per phase 1.9
SLEW_RATEx[2:0] = 110, COUT-TOTAL_BUCK < 500 µF per phase 0.94
SLEW_RATEx[2:0] = 111, COUT-TOTAL_BUCK < 500 µF per phase 0.47
IPFM-PWM PFM-to-PWM - current threshold(5) 550 mA
IPWM-PFM PWM-to-PFM - current threshold(5) 290 mA
IADD Phase adding level (dual-phase output) From 1-phase to 2-phase 1000 mA
ISHED Phase shedding level (dual-phase output) From 2-phase to 1-phase 650 mA
RDIS_Bx Output pulldown resistance Regulator disabled 150 250 350 Ω
Output voltage monitoring for PGOOD pin and for power-good Interrupt V(VIN_Bx) and V(VANA) fixed 3.7 V
Overvoltage threshold (compared to DC output voltage level, VVOUT_Bx_DC) 39 50 64 mV
Undervoltage threshold (compared to DC output voltage level, VVOUT_Bx_DC) –53 –40 –29
Deglitch time during operation and after voltage change 4 15 µs
Gating time for PGOOD signal after regulator enable or voltage change PGOOD_MODE = 0 800 µs
LDO REGULATORS
VIN_LDOx Input voltage range for LDO power inputs VIN_LDOx can be higher or lower than V(VANA) 2.5 3.7 5.5 V
VOUT_LDOx Output voltage Programmable voltage range 0.8 3.3 V
Step size 0.1
IOUT_LDOx Output current 300 mA
Dropout voltage V(VIN_LDOx) – V(VOUT_LDOx), IOUT = IOUT(max), Programmed output voltage is higher than V(VIN_LDOx) 200 mV
VOUT_LDO_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process, temperature VOUT < 1 V –20 20 mV
VOUT ≥ 1 V –2% 2%
DCLNR DC line regulation IOUT = 1 mA 0.1 %/V
DCLDR DC load regulation IOUT = 1 mA to IOUT(max) 0.8%
TLDSR Transient load step response IOUT = 1 mA to 300 mA, TR = TF = 1 µs –50/+40 mV
TLNSR Transient line response V(VIN_LDOx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) ±7 mV
PSRR Power supply ripple rejection ƒ = 10 kHz, IOUT = IOUT(max) 53 dB
Noise 10 Hz < F < 100 kHz, IOUT = IOUT(max) 82 µVrms
ISHORT(LDOx) LDO current limit VOUT = 0 V 400 500 600 mA
Start-up time From enable to valid output voltage 300 µs
Slew rate during start-up 15 mV/µs
RDIS_LDOx Output pulldown resistance Regulator disabled 150 250 350 Ω
Output voltage monitoring for PGOOD pin and for power-good interrupt Overvoltage monitoring, voltage rising (compared to DC output voltage level, VOUT_LDO_DC) 106% 108% 110%
Overvoltage monitoring, hysteresis 3% 3.5% 4%
Undervoltage monitoring, voltage falling (compared to DC output voltage level, VOUT_LDO_DC) 90% 92% 94%
Undervoltage monitoring, hysteresis 3% 3.5% 4%
Deglitch time during operation and after voltage change 4 15 µs
Gating time for PGOOD signal after regulator enable or voltage change PGOOD_MODE = 0 800 µs
EXTERNAL CLOCK AND PLL
fEXT_CLK External input clock(6) Nominal frequency 1 24 MHz
Nominal frequency step size 1
Required accuracy from nominal frequency –30% 10%
External clock detection Delay for missing clock detection 1.8 µs
Delay and debounce for clock detection 20
Clock change delay (internal to external) Delay from valid clock detection to use of external clock 600 µs
PLL output clock jitter Cycle to cycle 300 ps, p-p
PROTECTION FUNCTIONS
Thermal warning Temperature rising, TDIE_WARN_LEVEL = 0 115 125 135 °C
Temperature rising, TDIE_WARN_LEVEL = 1 127 137 147
Hysteresis 20
Thermal shutdown Temperature rising 140 150 160 °C
Hysteresis 20
VANAOVP VANA overvoltage Voltage rising 5.6 5.8 6.1 V
Voltage falling 5.45 5.73 5.96
Hysteresis 40 mV
VANAUVLO VANA undervoltage lockout Voltage rising 2.51 2.63 2.75 V
Voltage falling 2.5 2.6 2.7
Buck short-circuit detection Threshold 280 360 440 mV
LDO short-circuit detection Threshold 190 300 450 mV
LOAD CURRENT MEASUREMENT FOR BUCK REGULATORS
Current measurement range Maximum code 10.22 A
Resolution LSB 20 mA
Measurement accuracy IOUT > 1 A per phase <10%
Measurement time PFM mode (automatically changing to PWM mode for the measurement) 45 µs
PWM mode 4
CURRENT CONSUMPTION
Standby current consumption, regulators disabled 9 µA
Active current consumption, one buck regulator enabled in auto mode, internal RC oscillator, PGOOD monitoring enabled Single-phase output: IOUT_Bx = 0 mA, not switching 58 µA
Active current consumption, two buck regulators enabled in auto mode, internal RC oscillator, PGOOD monitoring enabled Single-phase output: IOUT_Bx = 0 mA, not switching 100 µA
Active current consumption, one buck regulator enabled in auto mode, internal RC oscillator, PGOOD monitoring enabled Dual-phase output: IOUT_Bx = 0 mA, not switching 72 µA
Active current consumption during PWM operation, one buck regulator enabled Single-phase output: IOUT_Bx = 0 mA 15 mA
Active current consumption during PWM operation, two buck regulators enabled Single-phase output: IOUT_Bx = 0 mA 30 mA
Active current consumption during PWM operation, buck regulator enabled Dual-phase output: IOUT_Bx = 0 mA 15 mA
LDO regulator enabled Additional current consumption per LDO, IOUT_LDOx = 0 mA 86 µA
PLL and clock detector current consumption fEXT_CLK = 1 MHz, Additional current consumption when enabled 2 mA
DIGITAL INPUT SIGNALS EN, SCL, SDA, CLKIN
VIL Input low level 0.4 V
VIH Input high level 1.2
VHYS Hysteresis of Schmitt Trigger inputs 10 80 200 mV
EN/CLKIN pulldown resistance EN_PD/CLKIN_PD = 1 500
DIGITAL OUTPUT SIGNALS nINT, SDA
VOL Output low level nINT: ISOURCE = 2 mA 0.4 V
SDA: ISOURCE = 20 mA 0.4 V
RP External pullup resistor for nINT To VIO Supply 10 kΩ
DIGITAL OUTPUT SIGNALS PGOOD, GPO, GPO2
VOL Output low level ISOURCE = 2 mA 0.4 V
VOH Output high level, configured to push-pull ISINK = 2 mA VVANA – 0.4 VVANA V
VPU Supply voltage for external pullup resistor, configured to open-drain VVANA V
RPU External pullup resistor, configured to open-drain 10 kΩ
ALL DIGITAL INPUTS
ILEAK Input current All logic inputs over pin voltage range −1 1 µA
All voltage values are with respect to network ground.
Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely norm.
The maximum output current can be limited by the forward current limit ILIM FWD. The power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.
The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current.
The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage and the inductor current level.
The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.