SNVSBK2 September   2019 LP8733

PRODUCTION DATA.  

  1. Features
    1.     Simplified Schematic
  2. Applications
  3. Description
    1.     DC/DC Efficiency vs Output Current
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Dual-Phase Operation and Phase-Adding/Shedding
        3. 7.3.1.3 Transition Between PWM and PFM Modes
        4. 7.3.1.4 Dual-Phase Switcher Configurations
        5. 7.3.1.5 Buck Converter Load Current Measurement
        6. 7.3.1.6 Spread-Spectrum Mode
      2. 7.3.2  Sync Clock Functionality
      3. 7.3.3  Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4  Power-Up
      5. 7.3.5  Regulator Control
        1. 7.3.5.1 Enabling and Disabling Regulators
        2. 7.3.5.2 Changing Output Voltage
      6. 7.3.6  Enable and Disable Sequences
      7. 7.3.7  Device Reset Scenarios
      8. 7.3.8  Diagnosis and Protection Features
        1. 7.3.8.1 Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1 PGOOD Pin Gated Mode
          2. 7.3.8.1.2 PGOOD Pin Continuous Mode
        2. 7.3.8.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1 Output Power Limit
          2. 7.3.8.2.2 Thermal Warning
        3. 7.3.8.3 Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2 Overvoltage Protection
          3. 7.3.8.3.3 Thermal Shutdown
        4. 7.3.8.4 Fault (Power Down)
          1. 7.3.8.4.1 Undervoltage Lockout
      9. 7.3.9  Operation of the GPO Signals
      10. 7.3.10 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
          1. Table 8. DEV_REV Register Field Descriptions
        2. 7.6.1.2  OTP_REV
          1. Table 9. OTP_REV Register Field Descriptions
        3. 7.6.1.3  BUCK0_CTRL_1
          1. Table 10. BUCK0_CTRL_1 Register Field Descriptions
        4. 7.6.1.4  BUCK0_CTRL_2
          1. Table 11. BUCK0_CTRL_2 Register Field Descriptions
        5. 7.6.1.5  BUCK1_CTRL_1
          1. Table 12. BUCK1_CTRL_1 Register Field Descriptions
        6. 7.6.1.6  BUCK1_CTRL_2
          1. Table 13. BUCK1_CTRL_2 Register Field Descriptions
        7. 7.6.1.7  BUCK0_VOUT
          1. Table 14. BUCK0_VOUT Register Field Descriptions
        8. 7.6.1.8  BUCK1_VOUT
          1. Table 15. BUCK1_VOUT Register Field Descriptions
        9. 7.6.1.9  LDO0_CTRL
          1. Table 16. LDO0_CTRL Register Field Descriptions
        10. 7.6.1.10 LDO1_CTRL
          1. Table 17. LDO1_CTRL Register Field Descriptions
        11. 7.6.1.11 LDO0_VOUT
          1. Table 18. LDO0_VOUT Register Field Descriptions
        12. 7.6.1.12 LDO1_VOUT
          1. Table 19. LDO1_VOUT Register Field Descriptions
        13. 7.6.1.13 BUCK0_DELAY
          1. Table 20. BUCK0_DELAY Register Field Descriptions
        14. 7.6.1.14 BUCK1_DELAY
          1. Table 21. BUCK1_DELAY Register Field Descriptions
        15. 7.6.1.15 LDO0_DELAY
          1. Table 22. LDO0_DELAY Register Field Descriptions
        16. 7.6.1.16 LDO1_DELAY
          1. Table 23. LDO1_DELAY Register Field Descriptions
        17. 7.6.1.17 GPO_DELAY
          1. Table 24. GPO_DELAY Register Field Descriptions
        18. 7.6.1.18 GPO2_DELAY
          1. Table 25. GPO2_DELAY Register Field Descriptions
        19. 7.6.1.19 GPO_CTRL
          1. Table 26. GPO_CTRL Register Field Descriptions
        20. 7.6.1.20 CONFIG
          1. Table 27. CONFIG Register Field Descriptions
        21. 7.6.1.21 PLL_CTRL
          1. Table 28. PLL_CTRL Register Field Descriptions
        22. 7.6.1.22 PGOOD_CTRL_1
          1. Table 29. PGOOD_CTRL_1 Register Field Descriptions
        23. 7.6.1.23 PGOOD_CTRL_2
          1. Table 30. PGOOD_CTRL_2 Register Field Descriptions
        24. 7.6.1.24 PG_FAULT
          1. Table 31. PG_FAULT Register Field Descriptions
        25. 7.6.1.25 RESET
          1. Table 32. RESET Register Field Descriptions
        26. 7.6.1.26 INT_TOP_1
          1. Table 33. INT_TOP_1 Register Field Descriptions
        27. 7.6.1.27 INT_TOP_2
          1. Table 34. INT_TOP_2 Register Field Descriptions
        28. 7.6.1.28 INT_BUCK
          1. Table 35. INT_BUCK Register Field Descriptions
        29. 7.6.1.29 INT_LDO
          1. Table 36. INT_LDO Register Field Descriptions
        30. 7.6.1.30 TOP_STAT
          1. Table 37. TOP_STAT Register Field Descriptions
        31. 7.6.1.31 BUCK_STAT
          1. Table 38. BUCK_STAT Register Field Descriptions
        32. 7.6.1.32 LDO_STAT
          1. Table 39. LDO_STAT Register Field Descriptions
        33. 7.6.1.33 TOP_MASK_1
          1. Table 40. TOP_MASK_1 Register Field Descriptions
        34. 7.6.1.34 TOP_MASK_2
          1. Table 41. TOP_MASK_2 Register Field Descriptions
        35. 7.6.1.35 BUCK_MASK
          1. Table 42. BUCK_MASK Register Field Descriptions
        36. 7.6.1.36 LDO_MASK
          1. Table 43. LDO_MASK Register Field Descriptions
        37. 7.6.1.37 SEL_I_LOAD
          1. Table 44. SEL_I_LOAD Register Field Descriptions
        38. 7.6.1.38 I_LOAD_2
          1. Table 45. I_LOAD_2 Register Field Descriptions
        39. 7.6.1.39 I_LOAD_1
          1. Table 46. I_LOAD_1 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Input Capacitor Selection
        5. 8.2.1.5 LDO Output Capacitor Selection
        6. 8.2.1.6 Current Limit vs. Maximum Output Current
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

RHD Package
28-Pin VQFN With Thermal Pad
Top View
LP8733 Ballmap_33.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NUMBER NAME
1 VOUT_LDO0 P/O LDO0 output. If the LDO0 is not used, leave the pin floating.
2 FB_B0 A Output voltage feedback (positive) for Buck 0
3 FB_B1 A Output voltage feedback (positive) for Buck 1 in two single-phase configuration and output ground feedback (negative) for Buck 0 in dual-phase configuration
4 AGND G Ground
5 VANA P/I Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx.
6 EN D/I Programmable enable signal for regulators and GPOs. If the pin is not used, leave the pin floating.
7 VOUT_LDO1 P/O LDO1 output. If LDO1 is not used, leave the pin floating.
8 VIN_LDO1 P/I Power input for LDO1. If LDO1 is not used, connect the pin to VANA.
9 nINT D/O Open-drain interrupt output. Active LOW. If the pin is not used, connect the pin to ground.
10 CLKIN D/I/O External clock input. Alternative function is general-purpose digital output (GPO2). If the pin is not used, leave the pin floating.
11, 12 VIN_B1 P/I Input for Buck 1. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.
13, 14 SW_B1 P/O Buck 1 switch node. If the Buck 1 is not used, leave the pin floating.
15, 16 PGND_B1 P/G Power ground for Buck 1
17 SCL D/I Serial interface clock input for I2C access. Connect a pullup resistor. If the I2C interface is not used, connect the pin to Ground.
18 SDA D/I/O Serial interface data input and output for I2C access. Connect a pullup resistor. If the I2C interface is not used, connect the pin to Ground.
19 SGND G Ground
20, 21 PGND_B0 P/G Power ground for Buck 0
22, 23 SW_B0 P/O Buck 0 switch node. If the Buck 0 is not used, leave the pin floating.
24, 25 VIN_B0 P/I Input for Buck 0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.
26 GPO D/O General-purpose digital output. If the pin is not used, leave the pin floating.
27 PGOOD D/O Power-good indication signal. If the pin is not used, leave the pin floating.
28 VIN_LDO0 P/I Power input for LDO0. If the LDO0 is not used, connect the pin to VANA.
Thermal Pad Connect to PCB ground plane using multiple vias for good thermal performance.
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin