SNVSBK2 September   2019 LP8733

PRODUCTION DATA.  

  1. Features
    1.     Simplified Schematic
  2. Applications
  3. Description
    1.     DC/DC Efficiency vs Output Current
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Dual-Phase Operation and Phase-Adding/Shedding
        3. 7.3.1.3 Transition Between PWM and PFM Modes
        4. 7.3.1.4 Dual-Phase Switcher Configurations
        5. 7.3.1.5 Buck Converter Load Current Measurement
        6. 7.3.1.6 Spread-Spectrum Mode
      2. 7.3.2  Sync Clock Functionality
      3. 7.3.3  Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4  Power-Up
      5. 7.3.5  Regulator Control
        1. 7.3.5.1 Enabling and Disabling Regulators
        2. 7.3.5.2 Changing Output Voltage
      6. 7.3.6  Enable and Disable Sequences
      7. 7.3.7  Device Reset Scenarios
      8. 7.3.8  Diagnosis and Protection Features
        1. 7.3.8.1 Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1 PGOOD Pin Gated Mode
          2. 7.3.8.1.2 PGOOD Pin Continuous Mode
        2. 7.3.8.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1 Output Power Limit
          2. 7.3.8.2.2 Thermal Warning
        3. 7.3.8.3 Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2 Overvoltage Protection
          3. 7.3.8.3.3 Thermal Shutdown
        4. 7.3.8.4 Fault (Power Down)
          1. 7.3.8.4.1 Undervoltage Lockout
      9. 7.3.9  Operation of the GPO Signals
      10. 7.3.10 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
          1. Table 8. DEV_REV Register Field Descriptions
        2. 7.6.1.2  OTP_REV
          1. Table 9. OTP_REV Register Field Descriptions
        3. 7.6.1.3  BUCK0_CTRL_1
          1. Table 10. BUCK0_CTRL_1 Register Field Descriptions
        4. 7.6.1.4  BUCK0_CTRL_2
          1. Table 11. BUCK0_CTRL_2 Register Field Descriptions
        5. 7.6.1.5  BUCK1_CTRL_1
          1. Table 12. BUCK1_CTRL_1 Register Field Descriptions
        6. 7.6.1.6  BUCK1_CTRL_2
          1. Table 13. BUCK1_CTRL_2 Register Field Descriptions
        7. 7.6.1.7  BUCK0_VOUT
          1. Table 14. BUCK0_VOUT Register Field Descriptions
        8. 7.6.1.8  BUCK1_VOUT
          1. Table 15. BUCK1_VOUT Register Field Descriptions
        9. 7.6.1.9  LDO0_CTRL
          1. Table 16. LDO0_CTRL Register Field Descriptions
        10. 7.6.1.10 LDO1_CTRL
          1. Table 17. LDO1_CTRL Register Field Descriptions
        11. 7.6.1.11 LDO0_VOUT
          1. Table 18. LDO0_VOUT Register Field Descriptions
        12. 7.6.1.12 LDO1_VOUT
          1. Table 19. LDO1_VOUT Register Field Descriptions
        13. 7.6.1.13 BUCK0_DELAY
          1. Table 20. BUCK0_DELAY Register Field Descriptions
        14. 7.6.1.14 BUCK1_DELAY
          1. Table 21. BUCK1_DELAY Register Field Descriptions
        15. 7.6.1.15 LDO0_DELAY
          1. Table 22. LDO0_DELAY Register Field Descriptions
        16. 7.6.1.16 LDO1_DELAY
          1. Table 23. LDO1_DELAY Register Field Descriptions
        17. 7.6.1.17 GPO_DELAY
          1. Table 24. GPO_DELAY Register Field Descriptions
        18. 7.6.1.18 GPO2_DELAY
          1. Table 25. GPO2_DELAY Register Field Descriptions
        19. 7.6.1.19 GPO_CTRL
          1. Table 26. GPO_CTRL Register Field Descriptions
        20. 7.6.1.20 CONFIG
          1. Table 27. CONFIG Register Field Descriptions
        21. 7.6.1.21 PLL_CTRL
          1. Table 28. PLL_CTRL Register Field Descriptions
        22. 7.6.1.22 PGOOD_CTRL_1
          1. Table 29. PGOOD_CTRL_1 Register Field Descriptions
        23. 7.6.1.23 PGOOD_CTRL_2
          1. Table 30. PGOOD_CTRL_2 Register Field Descriptions
        24. 7.6.1.24 PG_FAULT
          1. Table 31. PG_FAULT Register Field Descriptions
        25. 7.6.1.25 RESET
          1. Table 32. RESET Register Field Descriptions
        26. 7.6.1.26 INT_TOP_1
          1. Table 33. INT_TOP_1 Register Field Descriptions
        27. 7.6.1.27 INT_TOP_2
          1. Table 34. INT_TOP_2 Register Field Descriptions
        28. 7.6.1.28 INT_BUCK
          1. Table 35. INT_BUCK Register Field Descriptions
        29. 7.6.1.29 INT_LDO
          1. Table 36. INT_LDO Register Field Descriptions
        30. 7.6.1.30 TOP_STAT
          1. Table 37. TOP_STAT Register Field Descriptions
        31. 7.6.1.31 BUCK_STAT
          1. Table 38. BUCK_STAT Register Field Descriptions
        32. 7.6.1.32 LDO_STAT
          1. Table 39. LDO_STAT Register Field Descriptions
        33. 7.6.1.33 TOP_MASK_1
          1. Table 40. TOP_MASK_1 Register Field Descriptions
        34. 7.6.1.34 TOP_MASK_2
          1. Table 41. TOP_MASK_2 Register Field Descriptions
        35. 7.6.1.35 BUCK_MASK
          1. Table 42. BUCK_MASK Register Field Descriptions
        36. 7.6.1.36 LDO_MASK
          1. Table 43. LDO_MASK Register Field Descriptions
        37. 7.6.1.37 SEL_I_LOAD
          1. Table 44. SEL_I_LOAD Register Field Descriptions
        38. 7.6.1.38 I_LOAD_2
          1. Table 45. I_LOAD_2 Register Field Descriptions
        39. 7.6.1.39 I_LOAD_1
          1. Table 46. I_LOAD_1 Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Input Capacitor Selection
        5. 8.2.1.5 LDO Output Capacitor Selection
        6. 8.2.1.6 Current Limit vs. Maximum Output Current
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Register Descriptions

The LP8733xx is controlled by a set of registers through the I2C-compatible interface. The device registers addresses and abbreviations are listed in Table 7. A more detailed description is given in the DEV_REV to I_LOAD_1 sections.

NOTE

This register map describes the default values for bits that are not read from OTP memory. The orderable code and the default register bit values are defined in part-number specific Technical Reference Manuals.

Table 7. Summary of LP8733xx Control Registers

Addr Register Read / Write D7 D6 D5 D4 D3 D2 D1 D0
0x00 DEV_REV R DEVICE_ID[1:0] Reserved - do not use
0x01 OTP_REV R OTP_ID[7:0]
0x02 BUCK0_
CTRL_1
R/W Reserved - do not use BUCK0_FPWM_MP BUCK0_FPWM BUCK0_RDIS_EN BUCK0_
EN_PIN_CTRL
BUCK0_EN
0x03 BUCK0_
CTRL_2
R/W Reserved - do not use BUCK0_ILIM[2:0] BUCK0_SLEW_RATE[2:0]
0x04 BUCK1_
CTRL_1
R/W Reserved - do not use BUCK1_FPWM BUCK1_RDIS_EN BUCK1_
EN_PIN_CTRL
BUCK1_EN
0x05 BUCK1_
CTRL_2
R/W Reserved - do not use BUCK1_ILIM[2:0] BUCK1_SLEW_RATE[2:0]
0x06 BUCK0_
VOUT
R/W BUCK0_VSET[7:0]
0x07 BUCK1_
VOUT
R/W BUCK1_VSET[7:0]
0x08 LDO0_
CTRL
R/W Reserved - do not use LDO0_RDIS_EN LDO0_
EN_PIN_CTRL
LDO0_EN
0x09 LDO1_
CTRL
R/W Reserved - do not use LDO1_RDIS_EN LDO1_
EN_PIN_CTRL
LDO1_EN
0x0A LDO0_
VOUT
R/W Reserved - do not use LDO0_VSET[4:0]
0x0B LDO1_
VOUT
R/W Reserved - do not use LDO1_VSET[4:0]
0x0C BUCK0_
DELAY
R/W BUCK0_SHUTDOWN_DELAY[3:0] BUCK0_STARTUP_DELAY[3:0]
0x0D BUCK1_
DELAY
R/W BUCK1_SHUTDOWN_DELAY[3:0] BUCK1_STARTUP_DELAY[3:0]
0x0E LDO0_
DELAY
R/W LDO0_SHUTDOWN_DELAY[3:0] LDO0_STARTUP_DELAY[3:0]
0x0F LDO1_
DELAY
R/W LDO1_SHUTDOWN_DELAY[3:0] LDO1_STARTUP_DELAY[3:0]
0x10 GPO_
DELAY
R/W GPO_SHUTDOWN_DELAY[3:0] GPO_STARTUP_DELAY[3:0]
0x11 GPO2_
DELAY
R/W GPO2_SHUTDOWN_DELAY[3:0] GPO2_STARTUP_DELAY[3:0]
0x12 GPO_
CTRL
R/W Reserved - do not use GPO2_OD GPO2_
EN_PIN_CTRL
GPO2_EN Reserved - do not use GPO_OD GPO_
EN_PIN_CTRL
GPO_EN
0x13 CONFIG R/W Reserved - do not use STARTUP_DELAY_SEL SHUTDOWN_DELAY_SEL CLKIN_PIN_SEL CLKIN_PD EN_PD TDIE
_WARN
_LEVEL
EN_
SPREAD
_SPEC
0x14 PLL_CTRL R/W Reserved - do not use EN_PLL Reserved - do not use EXT_CLK_FREQ[4:0]
0x15 PGOOD_CTRL_1 R/W PGOOD_POL PGOOD_OD PGOOD_WINDOW_LDO PGOOD_WINDOW_BUCK EN_PGOOD_LDO1 EN_PGOOD_LDO0 EN_PGOOD_BUCK1 EN_PGOOD_BUCK0
0x16 PGOOD_CTRL_2 R/W Reserved - do not use EN_PGOOD_TWARN PG_FAULT_GATES_PGOOD PGOOD_MODE
0x17 PG_FAULT R Reserved - do not use PG_FAULT_LDO1 PG_FAULT_LDO0 PG_FAULT_BUCK1 PG_FAULT_BUCK0
0x18 RESET R/W Reserved - do not use SW_
RESET
0x19 INT_TOP_1 R/W PGOOD_
INT
INT_
LDO
INT_
BUCK
SYNC_
CLK_INT
TDIE_SD_INT TDIE_
WARN_INT
OVP_INT I_MEAS_
INT
0x1A INT_TOP_2 R/W Reserved - do not use RESET_
REG_INT
0x1B INT_BUCK R/W Reserved - do not use BUCK1_
PG_INT
BUCK1_
SC_INT
BUCK1_
ILIM_INT
Reserved - do not use BUCK0_
PG_INT
BUCK0_
SC_INT
BUCK0_
ILIM_INT
0x1C INT_LDO R/W Reserved - do not use LDO1_
PG_INT
LDO1_
SC_INT
LDO1_
ILIM_INT
Reserved - do not use LDO0_
PG_INT
LDO0_
SC_INT
LDO0_
ILIM_INT
0x1D TOP_
STAT
R PGOOD_STAT Reserved - do not use SYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_
WARN_
STAT
OVP_
STAT
Reserved - do not use
0x1E BUCK_STAT R BUCK1_
STAT
BUCK1_
PG_STAT
Reserved - do not use BUCK1_
ILIM_STAT
BUCK0_
STAT
BUCK0_
PG_STAT
Reserved - do not use BUCK0_
ILIM_STAT
0x1F LDO_STAT R LDO1_
STAT
LDO1_
PG_STAT
Reserved - do not use LDO1_
ILIM_STAT
LDO0_
STAT
LDO0_
PG_STAT
Reserved - do not use LDO0_
ILIM_STAT
0x20 TOP_
MASK_1
R/W PGOOD_
INT_MASK
Reserved - do not use SYNC_CLK
_MASK
Reserved - do not use TDIE_WARN_MASK Reserved - do not use I_MEAS_
MASK
0x21 TOP_
MASK_2
R/W Reserved - do not use RESET_
REG_MASK
0x22 BUCK_MASK R/W BUCK1_PGF_MASK BUCK1_PGR_MASK Reserved - do not use BUCK1_
ILIM_
MASK
BUCK0_PGF_MASK BUCK0_PGR_MASK Reserved - do not use BUCK0_
ILIM_
MASK
0x23 LDO_MASK R/W LDO1_PGF_MASK LDO1_PGR_MASK Reserved - do not use LDO1_
ILIM_
MASK
LDO0_PGF_MASK LDO0_PGR_MASK Reserved - do not use LDO0_
ILIM_
MASK
0x24 SEL_I_
LOAD
R/W Reserved - do not use LOAD_CURRENT_
BUCK_SELECT
0x25 I_LOAD_2 R Reserved - do not use BUCK_LOAD_CURRENT[8]
0x26 I_LOAD_1 R BUCK_LOAD_CURRENT[7:0]