SNVSBK2 September 2019 LP8733
The LP8733xx device contains a CLKIN input to synchronize the switching clock of the buck regulators with the external clock. The block diagram of the clocking and PLL module is shown in Figure 12. Depending on the EN_PLL bit in the PLL_CTRL register and the external clock availability, the external clock is selected and interrupt is generated as shown in Table 2. The interrupt can be masked with the SYNC_CLK_MASK bit in the TOP_MASK_1 register. The nominal frequency of the external input clock is set by the EXT_CLK_FREQ[4:0] bits in the PLL_CTRL register, and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy limits (–30%/+10%) of the selected frequency for valid clock detection.
The SYNC_CLK_INT interrupt in the INT_TOP_1 register is also generated in cases where the external clock is expected but is not available. These cases occur when EN_PLL is 1 during start-up (read OTP-to-standby transition) and during Buck regulator enable (standby-to-active transition).
|DEVICE OPERATION MODE||EN_PLL||PLL AND CLOCK DETECTOR STATE||INTERRUPT FOR EXTERNAL CLOCK||CLOCK|
|STANDBY||1||Enabled||When external clock appears or disappears||Automatic change to external clock when available|
|ACTIVE||1||Enabled||When external clock appears or disappears||Automatic change to external clock when available|