SNVSBK2 September 2019 LP8733
TOP_MASK_2 is shown in Table 41, Address: 0x21
|Reserved - do not use||RESET_REG
|7:1||Reserved - do not use||R/W||000 0000|
|R/W||X||Masking for register reset interrupt (RESET_REG_INT in INT_TOP_2 register):
0 - Interrupt is generated.
1 - Interrupt is not generated.
This change of this bit by I2C writing has no effect because it will be read from OTP memory during reset.