SNVSB22 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The LP8756x-Q1 is controlled by a set of registers through the I2C-compatible interface. The device registers, their addresses, and their abbreviations are listed in Table 9. A more detailed description is given in the OTP_REV to GPIO_OUT sections.
NOTE
This register map describes the default values for bits that are not read from OTP memory. The orderable code and the default register bit values are defined in part-number specific Technical Reference Manuals.
Address | Register | Access | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|
0x01 | OTP_REV | R | OTP_ID[7:0] | |||||||
0x02 | BUCK0_CTRL1 | R/W | EN_BUCK0 | EN_PIN_CTRL0 | BUCK0_EN_PINSELECT[1:0] | EN_ROOF_FLOOR0 | EN_RDIS0 | BUCK0_FPWM | BUCK0_FPWM_MP | |
0x03 | BUCK0_CTRL2 | R/W | Reserved | ILIM0[2:0] | SLEW_RATE0[2:0] | |||||
0x04 | BUCK1_CTRL1 | R/W | EN_BUCK1 | EN_PIN_CTRL1 | BUCK1_EN_PINSELECT[1:0] | EN_ROOF_FLOOR1 | EN_RDIS1 | BUCK1_FPWM | Reserved | |
0x05 | BUCK1_CTRL2 | R/W | Reserved | ILIM1[2:0] | SLEW_RATE1[2:0] | |||||
0x06 | BUCK2_CTRL1 | R/W | EN_BUCK2 | EN_PIN_CTRL2 | BUCK2_EN_PINSELECT[1:0] | EN_ROOF_FLOOR2 | EN_RDIS2 | BUCK2_FPWM | BUCK2_FPWM_MP | |
0x07 | BUCK2_CTRL2 | R/W | Reserved | ILIM2[2:0] | SLEW_RATE2[2:0] | |||||
0x08 | BUCK3_CTRL1 | R/W | EN_BUCK3 | EN_PIN_CTRL3 | BUCK3_EN_PIN SELECT[1:0] | EN_ROOF_FLOOR3 | EN_RDIS3 | BUCK3_FPWM | Reserved | |
0x09 | BUCK3_CTRL2 | R/W | Reserved | ILIM3[2:0] | SLEW_RATE3[2:0] | |||||
0x0A | BUCK0_VOUT | R/W | BUCK0_VSET[7:0] | |||||||
0x0B | BUCK0_FLOOR_VOUT | R/W | BUCK0_FLOOR_VSET[7:0] | |||||||
0x0C | BUCK1_VOUT | R/W | BUCK1_VSET[7:0] | |||||||
0x0D | BUCK1_FLOOR_VOUT | R/W | BUCK1_FLOOR_VSET[7:0] | |||||||
0x0E | BUCK2_VOUT | R/W | BUCK2_VSET[7:0] | |||||||
0x0F | BUCK2_FLOOR_VOUT | R/W | BUCK2_FLOOR_VSET[7:0] | |||||||
0x10 | BUCK3_VOUT | R/W | BUCK3_VSET[7:0] | |||||||
0x11 | BUCK3_FLOOR_VOUT | R/W | BUCK3_FLOOR_VSET[7:0] | |||||||
0x12 | BUCK0_DELAY | R/W | BUCK0_SHUTDOWN_DELAY[3:0] | BUCK0_STARTUP_DELAY[3:0] | ||||||
0x13 | BUCK1_DELAY | R/W | BUCK1_SHUTDOWN_DELAY[3:0] | BUCK1_STARTUP_DELAY[3:0] | ||||||
0x14 | BUCK2_DELAY | R/W | BUCK2_SHUTDOWN_DELAY[3:0] | BUCK2_STARTUP_DELAY[3:0] | ||||||
0x15 | BUCK3_DELAY | R/W | BUCK3_SHUTDOWN_DELAY[3:0] | BUCK3_STARTUP_DELAY[3:0] | ||||||
0x16 | GPIO2_DELAY | R/W | GPIO2_SHUTDOWN_DELAY[3:0] | GPIO2_STARTUP_DELAY[3:0] | ||||||
0x17 | GPIO3_DELAY | R/W | GPIO3_SHUTDOWN_DELAY[3:0] | GPIO3_STARTUP_DELAY[3:0] | ||||||
0x18 | RESET | R/W | Reserved | SW_RESET | ||||||
0x19 | CONFIG | R/W | DOUBLE_DELAY | CLKIN_PD | Reserved | EN3_PD | TDIE_WARN_LEVEL | EN2_PD | EN1_PD | Reserved |
0x1A | INT_TOP1 | R/W | Reserved | INT_BUCK23 | INT_BUCK01 | NO_SYNC_CLK | TDIE_SD | TDIE_WARN | INT_OVP | I_LOAD_READY |
0x1B | INT_TOP2 | R/W | Reserved | RESET_REG | ||||||
0x1C | INT_BUCK_0_1 | R/W | Reserved | BUCK1_PG_INT | BUCK1_SC_INT | BUCK1_ILIM_INT | Reserved | BUCK0_PG_INT | BUCK0_SC_INT | BUCK0_ILIM_INT |
0x1D | INT_BUCK_2_3 | R/W | Reserved | BUCK3_PG_INT | BUCK3_SC_INT | BUCK3_ILIM_INT | Reserved | BUCK2_PG_INT | BUCK2_SC_INT | BUCK2_ILIM_INT |
0x1E | TOP_STAT | R | Reserved | SYNC_CLK_STAT | TDIE_SD_STAT | TDIE_WARN_STAT | OVP_STAT | Reserved | ||
0x1F | BUCK_0_1_STAT | R | BUCK1_STAT | BUCK1_PG_STAT | Reserved | BUCK1_ILIM_STAT | BUCK0_STAT | BUCK0_PG_STAT | Reserved | BUCK0_ILIM_STAT |
0x20 | BUCK_2_3_STAT | R | BUCK3_STAT | BUCK3_PG_STAT | Reserved | BUCK3_ILIM_STAT | BUCK2_STAT | BUCK2_PG_STAT | Reserved | BUCK2_ILIM_STAT |
0x21 | TOP_MASK1 | R/W | Reserved | Reserved | SYNC_CLK_MASK | Reserved | TDIE_WARN_MASK | Reserved | I_LOAD_READY_MASK | |
0x22 | TOP_MASK2 | R/W | Reserved | RESET_REG_MASK | ||||||
0x23 | BUCK_0_1_MASK | R/W | Reserved | BUCK1_PG_MASK | Reserved | BUCK1_ILIM_MASK | Reserved | BUCK0_PG_MASK | Reserved | BUCK0_ILIM_MASK |
0x24 | BUCK_2_3_MASK | R/W | Reserved | BUCK3_PG_MASK | Reserved | BUCK3_ILIM_MASK | Reserved | BUCK2_PG_MASK | Reserved | BUCK2_ILIM_MASK |
0x25 | SEL_I_LOAD | R/W | Reserved | LOAD_CURRENT_BUCK_SELECT[1:0] | ||||||
0x26 | I_LOAD_2 | R | Reserved | BUCK_LOAD_CURRENT[9:8] | ||||||
0x27 | I_LOAD_1 | R | BUCK_LOAD_CURRENT[7:0] | |||||||
0x28 | PGOOD_CTRL1 | R/W | PG3_SEL[1:0] | PG2_SEL[1:0] | PG1_SEL[1:0] | PG0_SEL[1:0] | ||||
0x29 | PGOOD_CTRL2 | R/W | HALF_DELAY | EN_PG0_NINT | PGOOD_SET_DELAY | EN_PGFLT_STAT | Reserved | PGOOD_WINDOW | PGOOD_OD | PGOOD_POL |
0x2A | PGOOD_FLT | R | PG3_FLT | PG2_FLT | PG1_FLT | PG0_FLT | ||||
0x2B | PLL_CTRL | R/W | PLL_MODE[1:0] | Reserved | EXT_CLK_FREQ[4:0] | |||||
0x2C | PIN_FUNCTION | R/W | EN_SPREAD_SPEC | EN_PIN_CTRL_GPIO3 | EN_PIN_SELECT_GPIO3 | EN_PIN_CTRL_GPIO2 | EN_PIN_SELECT_GPIO2 | GPIO3_SEL | GPIO2_SEL | GPIO1_SEL |
0x2D | GPIO_CONFIG | R/W | Reserved | GPIO3_OD | GPIO2_OD | GPIO1_OD | Reserved | GPIO3_DIR | GPIO2_DIR | GPIO1_DIR |
0x2E | GPIO_IN | R | Reserved | GPIO3_IN | GPIO2_IN | GPIO1_IN | ||||
0x2F | GPIO_OUT | R/W | Reserved | GPIO3_OUT | GPIO2_OUT | GPIO1_OUT |