SNVSA05A December   2019  – August 2021 LP875701-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1 Multi-Phase DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Multiphase Switcher Configurations
        3. 7.3.1.3 Buck Converter Load-Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. 7.3.4.1 Enabling and Disabling Regulators
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnosis and Protection Features
        1. 7.3.7.1 Power-Good Information (PGOOD pin)
        2. 7.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.7.2.1 Output Power Limit
          2. 7.3.7.2.2 Thermal Warning
        3. 7.3.7.3 Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2 Overvoltage Protection
          3. 7.3.7.3.3 Thermal Shutdown
        4. 7.3.7.4 Fault (Power Down)
          1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 GPIO Signal Operation
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1.       53
        2. 7.6.1.1  DEV_REV
        3. 7.6.1.2  OTP_REV
        4. 7.6.1.3  BUCK0_CTRL1
        5. 7.6.1.4  BUCK0_DELAY
        6. 7.6.1.5  GPIO2_DELAY
        7. 7.6.1.6  GPIO3_DELAY
        8. 7.6.1.7  RESET
        9. 7.6.1.8  CONFIG
        10. 7.6.1.9  INT_TOP1
        11. 7.6.1.10 INT_TOP2
        12. 7.6.1.11 INT_BUCK_0_1
        13. 7.6.1.12 INT_BUCK_2_3
        14. 7.6.1.13 TOP_STAT
        15. 7.6.1.14 BUCK_0_1_STAT
        16. 7.6.1.15 BUCK_2_3_STAT
        17. 7.6.1.16 TOP_MASK1
        18. 7.6.1.17 TOP_MASK2
        19. 7.6.1.18 BUCK_0_1_MASK
        20. 7.6.1.19 BUCK_2_3_MASK
        21. 7.6.1.20 SEL_I_LOAD
        22. 7.6.1.21 I_LOAD_2
        23. 7.6.1.22 I_LOAD_1
        24. 7.6.1.23 PGOOD_CTRL1
        25. 7.6.1.24 PGOOD_CTRL2
        26. 7.6.1.25 PGOOD_FLT
        27. 7.6.1.26 PLL_CTRL
        28. 7.6.1.27 PIN_FUNCTION
        29. 7.6.1.28 GPIO_CONFIG
        30. 7.6.1.29 GPIO_IN
        31. 7.6.1.30 GPIO_OUT
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Input Capacitor Selection
        3. 8.2.1.3 Output Capacitor Selection
        4. 8.2.1.4 Snubber Components
        5. 8.2.1.5 Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

–40°C ≤ TJ ≤ +140°C, CPOL = 122 µF/phase, specified VVANA, VVIN_Bx , VNRST, VVOUT_Bx, and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1.0 V, unless otherwise noted.(1)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
EXTERNAL COMPONENTS
CINInput filtering capacitanceConnected from VIN_Bx to PGND_Bx1.910µF
COUTOutput filtering capacitance per phase, local1022µF
CPOLPoint-of-load (POL) capacitance per phase122µF
COUT-TOTALTotal output capacitance(2) (local and POL)4-phase output4001500µF
ESRCESR of the input and output capacitor1 MHz ≤ f ≤ 10 MHz210mΩ
LInductor value and tolerance of the inductor0.33µH
–30%30%
DCRLInductor DCR20mΩ
BUCK REGULATOR
VVIN_BxInput voltage range2.85.5V
IOUTOutput current(3)The maximum output current from device is 10A regardless of device phase configurations.4-phase output, VIN ≥ 3 V10A
4-phase output, 2.8 V ≤ VIN < 3 V7.2
Input and output voltage difference
Minimum voltage between VIN_x and VOUT to fulfill the electrical characteristics		0.5V
VVOUT_DCDC output voltage and accuracy, includes voltage reference, DC load and line regulations, process, and temperatureVIN= 3.3 V +/- 5% , 5 V +/- 5%, forced PWM mode, forced 4-phase operation, fSW= 3 MHz +/- 10% (either through internal or external clock), in case external clock is used: spread-spectrum disabled0.98511.015V
Ripple voltage4-phase output, forced PWM mode, ESRC < 2 mΩ, L = 0.33 µH3mVp-p
DCLNRDC line regulationIOUT = IOUT(max)0.1%/V
DCLDRDC load regulation in PWM mode0 A ≤ IOUT ≤ IOUT(max)0.01%/A
TRLDSRTransient load step response in PWM modeVIN = 5 V +/- 5%, fSW= 3 MHz +/- 10% (either through internal or external clock), in case external clock is used: spread-spectrum disabled, forced 4-phase operation, forced PWM mode
1.5 A ≤ IOUT ≤ 7.5 A, tr = tf = 1 µs, COUT = 22 µF/phase, L = 0.33 µH, CPOL = 122 µF/phase		±12mV
VIN = 3.3 V +/- 5%, fSW= 3 MHz +/- 10% (either through internal or external clock), in case external clock is used: spread-spectrum disabled, forced 4-phase operation, forced PWM mode
1.5 A ≤ IOUT ≤ 7.5 A, tr = tf = 1 µs, COUT = 22 µF/phase, L = 0.33 µH, CPOL = 122 µF/phase		±15
TRLNSRTransient line responseVVIN_Bx stepping 3.15 V ↔ 3.4 V, tr = tf = 10 µs, IOUT = IOUT(max)±2mV
ILIM FWDForward current limit for each phase (peak for each switching cycle)VVIN_Bx ≥ 3 V
Forward current limit for each phase set to 3.5A (ILIMx[2:0]=4h)		3.33.84.2A
2.8 V ≤ VVIN_Bx < 3 V
Forward current limit for each phase set to 3.5A (ILIMx[2:0]=4h)		2.83.84.2
ILIM NEGNegative current limit per phase (peak for each switching cycle)1.622.4A
RDS(ON) HS FETOn-resistance, high-side FETEach phase, between VIN_Bx and SW_Bx pins, I = 1 A2965mΩ
RDS(ON) LS FETOn-resistance, low-side FETEach phase, between SW_Bx and PGND_Bx pins, I = 1 A1735mΩ
fSWSwitching frequency, PWM mode2.733.3MHz
Current balancing for multiphase outputsCurrent mismatch between phases, IOUT > 1 A/phase10%
Start-Up time (soft start)From ENx to VOUT = 0.35 V (slew-rate control begins), COUT_TOTAL = 144 µF/phase200µs
Output voltage slew-rate(4)3.233.84.4mV/µs
Output pulldown resistanceRegulator disabled160230300Ω
Output voltage monitoring for PGOOD pinOvervoltage monitoring (compared to DC output-voltage level, VVOUT_DC)395064mV
Undervoltage monitoring (compared to DC output-voltage level, VVOUT_DC)–53–40–29
Deglitch time during regulator enable PGOOD_SET_DELAY = 0h4710µs
Deglitch time during regulator enable PGOOD_SET_DELAY = 1h101113ms
Deglitch time during operation and after voltage change4710µs
Power-good threshold for interrupt BUCKx_PG_INT, difference from final voltageRising ramp voltage, enable or voltage change–20–14–8mV
Falling ramp voltage, voltage change81420
Power-good threshold for status bit BUCKx_PG_STATDuring operation, status signal is forced to 0h during voltage change–20–14–8mV
EXTERNAL CLOCK AND PLL
Nominal frequency of the external input clock124MHz
Nominal frequency step size of the external input clock1MHz
Required accuracy from nominal frequency of the external input clock–30%10%
Delay time for missing external clock detection1.8µs
Delay and debounce time for external clock detection20µs
Clock change delay (internal to external)
delay from valid clock detection to use of external clock		600µs
Cycle-to-cycle PLL output clock jitter300ps, p-p
PROTECTION FUNCTIONS
Thermal warningTemperature rising, TDIE_WARN_LEVEL = 0h115125135°C
Temperature rising, TDIE_WARN_LEVEL = 1h127137147
Thermal warning hysteresis20°C
Thermal shutdownTemperature rising140150160°C
Thermal shutdown hysteresis20°C
VANAOVPVANA overvoltageVoltage rising5.65.86.1V
Voltage falling5.455.735.96
VANA overvoltage hysteresis40mV
VANAUVLOVANA undervoltage lockoutVoltage rising2.512.632.75V
Voltage falling2.52.62.7
LOAD CURRENT MEASUREMENT
Current measurement rangeOutput current for maximum code 20.47A
ResolutionLSB20mA
Measurement accuracyIOUT > 1 A<10%
Measurement timePWM mode4µs
CURRENT CONSUMPTION
Shutdown current consumptionFrom VANA and VIN_Bx pins, NRST = 0 V, VANA = VIN_Bx = 3.7 V1.4µA
Standby current consumptionFrom VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, regulators disabled6.7µA
Active current consumption during PWM operationTotal current for forced 4-phase operation, VIN = 3.3 V70mA
Total current for forced 4-phase operation, VIN = 5 V103
PLL and clock detector current consumptionAdditional current consumption when internal RC oscillator, clock detector and PLL are enabled2mA
DIGITAL INPUT SIGNALS: NRST, EN1, EN2, EN3, EN4, SCL, SDA, GPIO1, GPIO2, GPIO3, CLKIN
VILInput low level0.4V
VIHInput high level1.2V
VHYSHysteresis of Schmitt trigger inputs1077200mV
ENx pulldown resistanceENx_PD = 1h500kΩ
NRST pulldown resistanceAlways present65011501700kΩ
DIGITAL OUTPUT SIGNALS: nINT
VOLOutput low levelISOURCE = 2 mA0.4V
RPExternal pullup resistorTo VIO supply10kΩ
DIGITAL OUTPUT SIGNALS: SDA
VOLOutput low levelISOURCE = 10 mA0.4V
DIGITAL OUTPUT SIGNALS: PGOOD, GPIO1, GPIO2, GPIO3
VOLOutput low levelISOURCE = 2 mA0.4V
VOHOutput high level, configured to push-pullISINK = 2 mAVVANA – 0.4VVANAV
VPUSupply voltage for external pull-up resistor, configured to open-drainVVANAV
RPUExternal pullup resistor, configured to open-drain10kΩ
ALL DIGITAL INPUTS
ILEAKInput currentAll logic inputs over pin voltage range (except NRST)−11µA
(1) All voltage values are with respect to network ground.
(2) The output voltage slew-rate setting limits the maximum output capacitance.
(3) The maximum output current can be limited by the forward current limit ILIM FWD and by the junction temperature. The power dissipation inside the die depends on the length of the current pulse and efficiency and the junction temperature may increase to thermal shutdown level if the board and ambient temperatures are high.
(4) Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates.