SLLSFV6B January   2024  – September 2025 MCF8315C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Output Stage
      2. 6.3.2  Device Interface
        1. 6.3.2.1 Interface - Control and Monitoring
        2. 6.3.2.2 I2C Interface
      3. 6.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 6.3.3.1 Buck in Inductor Mode
        2. 6.3.3.2 Buck in Resistor mode
        3. 6.3.3.3 Buck Regulator with External LDO
        4. 6.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 6.3.3.5 Mixed Mode Buck Operation and Control
        6. 6.3.3.6 Buck Under Voltage Protection
        7. 6.3.3.7 Buck Over Current Protection
      4. 6.3.4  AVDD Linear Voltage Regulator
      5. 6.3.5  Charge Pump
      6. 6.3.6  Slew Rate Control
      7. 6.3.7  Cross Conduction (Dead Time)
      8. 6.3.8  Motor Control Input Sources
        1. 6.3.8.1 Analog Mode Motor Control
        2. 6.3.8.2 PWM Mode Motor Control
        3. 6.3.8.3 I2C based Motor Control
        4. 6.3.8.4 Frequency Mode Motor Control
        5. 6.3.8.5 Speed Profiles
          1. 6.3.8.5.1 Linear Reference Profiles
          2. 6.3.8.5.2 Staircase Reference Profiles
          3. 6.3.8.5.3 Forward-Reverse Reference Profiles
      9. 6.3.9  Starting the Motor Under Different Initial Conditions
        1. 6.3.9.1 Case 1 – Motor is Stationary
        2. 6.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 6.3.10 Motor Start Sequence (MSS)
        1. 6.3.10.1 Initial Speed Detect (ISD)
        2. 6.3.10.2 Motor Resynchronization
        3. 6.3.10.3 Reverse Drive
          1. 6.3.10.3.1 Reverse Drive Tuning
      11. 6.3.11 Motor Start-up
        1. 6.3.11.1 Align
        2. 6.3.11.2 Double Align
        3. 6.3.11.3 Initial Position Detection (IPD)
          1. 6.3.11.3.1 IPD Operation
          2. 6.3.11.3.2 IPD Release Mode
          3. 6.3.11.3.3 IPD Advance Angle
        4. 6.3.11.4 Slow First Cycle Start-up
        5. 6.3.11.5 Open loop
        6. 6.3.11.6 Transition from Open to Closed Loop
      12. 6.3.12 Closed Loop Operation
        1. 6.3.12.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 6.3.12.2 Speed PI Control
        3. 6.3.12.3 Current PI Control
        4. 6.3.12.4 Torque Mode
        5. 6.3.12.5 Overmodulation
      13. 6.3.13 Motor Parameters
        1. 6.3.13.1 Motor Resistance
        2. 6.3.13.2 Motor Inductance
        3. 6.3.13.3 Motor Back-EMF constant
      14. 6.3.14 Motor Parameter Extraction Tool (MPET)
      15. 6.3.15 Anti-Voltage Surge (AVS)
      16. 6.3.16 Active Braking
      17. 6.3.17 Output PWM Switching Frequency
      18. 6.3.18 PWM Modulation Schemes
      19. 6.3.19 Dead Time Compensation
      20. 6.3.20 Motor Stop Options
        1. 6.3.20.1 Coast (Hi-Z) Mode
        2. 6.3.20.2 Low-Side Braking
        3. 6.3.20.3 Active Spin-Down
      21. 6.3.21 FG Configuration
        1. 6.3.21.1 FG Output Frequency
        2. 6.3.21.2 FG during open loop
        3. 6.3.21.3 FG during idle and fault
      22. 6.3.22 DC Bus Current Limit
      23. 6.3.23 Protections
        1. 6.3.23.1  VM Supply Undervoltage Lockout
        2. 6.3.23.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 6.3.23.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 6.3.23.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 6.3.23.5  Overvoltage Protection (OVP)
        6. 6.3.23.6  Overcurrent Protection (OCP)
          1. 6.3.23.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 6.3.23.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 6.3.23.7  Buck Overcurrent Protection
        8. 6.3.23.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 6.3.23.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 6.3.23.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 6.3.23.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 6.3.23.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 6.3.23.9  Motor Lock (MTR_LCK)
          1. 6.3.23.9.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 6.3.23.9.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 6.3.23.9.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 6.3.23.9.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        10. 6.3.23.10 Motor Lock Detection
          1. 6.3.23.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.23.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 6.3.23.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 6.3.23.11 Minimum VM (undervoltage) Protection
        12. 6.3.23.12 Maximum VM (overvoltage) Protection
        13. 6.3.23.13 MPET Faults
        14. 6.3.23.14 IPD Faults
        15. 6.3.23.15 Thermal Warning (OTW)
        16. 6.3.23.16 Thermal Shutdown (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF Functionality
      2. 6.5.2 DAC output
      3. 6.5.3 Current Sense Output
      4. 6.5.4 Oscillator Source
        1. 6.5.4.1 External Clock Source
      5. 6.5.5 External Watchdog
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Transaction
        3. 6.6.2.3 I2C Read Transaction
        4. 6.6.2.4 I2C Communication Protocol Packet Examples
        5. 6.6.2.5 I2C Clock Stretching
        6. 6.6.2.6 CRC Byte Calculation
  8. 7 EEPROM (Non-Volatile) Register Map
    1. 7.1 Algorithm_Configuration Registers
    2. 7.2 Fault_Configuration Registers
    3. 7.3 Hardware_Configuration Registers
    4. 7.4 Internal_Algorithm_Configuration Registers
  9. 8 RAM (Volatile) Register Map
    1. 8.1 Fault_Status Registers
    2. 8.2 System_Status Registers
    3. 8.3 Device_Control Registers
    4. 8.4 Algorithm_Control Registers
    5. 8.5 Algorithm_Variables Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Curves
        1. 9.2.1.1 Motor startup
        2. 9.2.1.2 MPET
        3. 9.2.1.3 Dead time compensation
        4. 9.2.1.4 Auto handoff
        5. 9.2.1.5 Anti voltage surge (AVS)
        6. 9.2.1.6 Real time variable tracking using DACOUT
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Thermal Considerations
        1. 9.4.2.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.23 Protections

The MCF8315C-Q1 is protected from a host of fault events including motor lock, VM undervoltage, AVDD undervoltage, buck undervoltage, charge pump undervoltage, overtemperature and overcurrent events. Table 6-5 summarizes the response, recovery modes, power stage status, reporting mechanism for different faults.

Note:
  1. Actionable faults (latched or retry) are always reported on nFAULT pin (as logic low).
  2. Actionable faults (latched or retry) are reported on ALARM pin (as logic high) when ALARM_PIN_EN is set to 1b.
  3. Report only faults are reported on nFAULT (as logic low) only when ALARM_PIN_EN is set to 0b. When ALARM_PIN_EN is set to 1b, report only faults are reported only on ALARM pin (as logic high) while nFAULT stays high (via pull-up).
  4. Priority order for multi-fault scenarios is latched > slower retry time fault > faster retry time fault > report only fault. For example, if a latched and retry fault happen simultaneously, the device stays latched in fault mode until user issues clear fault command by writing 1b to CLR_FLT. If two retry faults with different retry times happen simultaneously, the device retries only after the longer (slower) retry time lapses.
  5. Recovery refers only to state of FETs (Hi-Z or active) after the fault condition is removed. Automatic indicates that the device automatically recovers (and FETs are active) when retry time lapses after the fault condition is removed. Latched indicates that the device waits for clearing of fault condition (by writing 1b to CLR_FLT bit) to make the FETs active again.
  6. Actionable (latched or retry) faults can take up to 200-ms after fault response (FETs in Hi-Z) to be reported on nFAULT pin (as logic low), ALARM pin (as logic high) and fault status registers.
  7. Latched faults can take up to 200-ms after CLR_FLT command is issued (over I2C) to be cleared.
Table 6-5 Fault Action and Response
FAULT CONDITION CONFIGURATION REPORT FETs DIGITAL RECOVERY
VM undervoltage VVM < VUVLO (falling) — — Hi-Z Disabled Automatic:
VVM > VUVLO (rising)
AVDD undervoltage VAVDD < VAVDD_UV (falling) — — Hi-Z Disabled Automatic:
VAVDD > VAVDD_UV (rising)
Buck undervoltage
(BUCK_UV)		 VFB_BK < VBK_UV (falling) — — Active/Hi-Z Active/Disabled Automatic:
VFB_BK > VBK_UV (rising)
Charge pump undervoltage
(VCP_UV)		 VCP < VCPUV (falling) — nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Automatic:
VVCP > VCPUV (rising)
Over Voltage Protection
(OVP)		 VVM > VOVP (rising) OVP_EN = 0b None Active Active No action
OVP_EN = 1b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Automatic:
VVM < VOVP
(falling)
Over Current Protection
(OCP)		 IPHASE > IOCP OCP_MODE = 00b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
OCP_MODE = 01b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Retry:
tRETRY
Buck Overcurrent Protection
(BUCK_OCP)		 IBK > IBK_OCP — — Hi-Z Disabled Automatic
Motor Lock
(MTR_LCK )		 Motor lock: Abnormal Speed; No Motor Lock; Abnormal BEMF MTR_LCK_MODE = 0000b or 0001b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MTR_LCK_MODE = 0010b nFAULT and CONTROLLER_FAULT_STATUS register High side brake Active Latched:
CLR_FLT
MTR_LCK_MODE = 0011b nFAULT and CONTROLLER_FAULT_STATUS register Low side brake Active Latched:
CLR_FLT
MTR_LCK_MODE = 0100b or 0101b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 0110b nFAULT and CONTROLLER_FAULT_STATUS register High side brake Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 0111b nFAULT and CONTROLLER_FAULT_STATUS register Low side brake Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 1000b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
MTR_LCK_MODE = 1xx1b None Active Active No action
Hardware Lock-Detection Current Limit
(HW_LOCK_LIMIT)
VSOX > HW_LOCK_ILIMIT HW_LOCK_ILIMIT_MODE = 0000b or 0001b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 0010b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 0011b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 0100b or 0101b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE = 0110b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE = 0111b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE= 1000b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
HW_LOCK_ILIMIT_MODE = 1xx1b None Active Active No action
Software Lock-Detection Current Limit
(LOCK_LIMIT)
VSOX > LOCK_ILIMIT LOCK_ILIMIT_MODE = 0000b or 0001b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0010b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0011b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0100b or 0101b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 0110b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 0111b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE= 1000b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
LOCK_ILIMIT_MODE = 1xx1b None Active Active No action
IPD Timeout Fault
(IPD_T1_FAULT and IPD_T2_FAULT)		 IPD TIME > 500ms (approx.), during IPD current ramp up or ramp down IPD_TIMEOUT_FAULT_EN = 0b — Active Active No action
IPD_TIMEOUT_FAULT_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry: tLCK_RETRY
IPD Frequency Fault
(IPD_FREQ_FAULT)		 IPD pulse before the current decay in previous IPD pulse IPD_FREQ_FAULT_EN = 0b — Active Active No action
IPD_FREQ_FAULT_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry: tLCK_RETRY
MPET IPD Fault
(MPET_IPD_FAULT)		 Same as IPD timeout fault during MPET R, L measurement — nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MPET Back-EMF Fault
(MPET_BEMF_FAULT)		 Motor back-EMF < STAT_DETECT_THR during MPET Ke and mechanical parameters measurement — nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
Maximum VM (overvoltage) fault VVM > MAX_VM_MOTOR, if MAX_VM_MOTOR ≠ 000b MAX_VM_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MAX_VM_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Automatic:
(VVM < MAX_VM_MOTOR - 1)-V
Minimum VM (undervoltage) fault VVM < MIN_VM_MOTOR, if MIN_VM_MOTOR ≠ 000b MIN_VM_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MIN_VM_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Automatic:
(VVM > MIN_VM_MOTOR + 0.5)-V
External Watchdog Watchdog tickle does not arrive before configured time interval when EXT_WDT_EN =1b. Refer Section 6.5.5 EXT_WDT_FAULT_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
EXT_WDT_FAULT_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
Bus Current Limit IVM > BUS_CURRENT_LIMIT. Refer Section 6.3.22 BUS_CURRENT_LIMIT_ENABLE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed/current will be restricted to limit DC bus current Active Automatic: Speed restriction is removed when IVM < BUS_CURRENT_LIMIT
Current Loop Saturation Indication of current loop saturation due to lower VVM SATURATION_FLAGS_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed may not reach speed reference Active Automatic: motor will reach reference operating point upon exiting saturation
Speed Loop Saturation Indication of speed loop saturation due to lower VVM, lower ILIMIT setting etc., SATURATION_FLAGS_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed may not reach speed reference Active Automatic: motor will reach reference operating point upon exiting saturation
Thermal warning
(OTW)		 TJ > TOTW OTW_REP = 0b — Active Active No action
OTW_REP = 1b nFAULT and GATE_DRIVER_FAULT_STATUS register Active Active No action
FET thermal shutdown
(TSD_FET)		 TJ > TTSD_FET — nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Automatic:
TJ < TTSD_FET – TTSD_FET_HYS