SLLSFI0C august   2021  – june 2023 MCF8316A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface Modes
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
        6. 7.3.3.6 Buck Undervoltage Protection
        7. 7.3.3.7 Buck Overcurrent Protection
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  SPEED Control
        1. 7.3.8.1 Analog-Mode Speed Control
        2. 7.3.8.2 PWM-Mode Speed Control
        3. 7.3.8.3 I2C based Speed Control
        4. 7.3.8.4 Frequency-Mode Speed Control
        5. 7.3.8.5 Speed Profiles
          1. 7.3.8.5.1 Linear Speed Profiles
          2. 7.3.8.5.2 Staircase Speed Profiles
          3. 7.3.8.5.3 Forward-Reverse Speed Profiles
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Overmodulation
      12. 7.3.12 Motor Parameters
        1. 7.3.12.1 Motor Resistance
        2. 7.3.12.2 Motor Inductance
        3. 7.3.12.3 Motor Back-EMF constant
      13. 7.3.13 Motor Parameter Extraction Tool (MPET)
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Output PWM Switching Frequency
      16. 7.3.16 Active Braking
      17. 7.3.17 PWM Modulation Schemes
      18. 7.3.18 Dead Time Compensation
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Recirculation Mode
        3. 7.3.19.3 Low-Side Braking
        4. 7.3.19.4 High-Side Braking
        5. 7.3.19.5 Active Spin-Down
        6. 7.3.19.6 Align Braking
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG Open-Loop and Lock Behavior
      21. 7.3.21 DC Bus Current Limit
      22. 7.3.22 Protections
        1. 7.3.22.1  VM Supply Undervoltage Lockout
        2. 7.3.22.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.22.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 7.3.22.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.22.5  Overvoltage Protection (OVP)
        6. 7.3.22.6  Overcurrent Protection (OCP)
          1. 7.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.22.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.22.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.22.7  Buck Overcurrent Protection
        8. 7.3.22.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 7.3.22.9  Thermal Warning (OTW)
        10. 7.3.22.10 Thermal Shutdown (TSD)
        11. 7.3.22.11 Motor Lock (MTR_LCK)
          1. 7.3.22.11.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.22.11.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.22.11.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.22.11.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        12. 7.3.22.12 Motor Lock Detection
          1. 7.3.22.12.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.22.12.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.22.12.3 Lock3: No-Motor Fault (NO_MTR)
        13. 7.3.22.13 MPET Faults
        14. 7.3.22.14 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 SOX Output
      3. 7.5.3 Oscillator Source
        1. 7.5.3.1 External Clock Source
      4. 7.5.4 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of MCF8316A I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Internal_Algorithm_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Device_Control Registers
      4. 7.8.4 Algorithm_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 MPET
        3. 8.2.1.3 Dead time compensation
        4. 8.2.1.4 Auto handoff
        5. 8.2.1.5 Motor stop – recirculation mode
        6. 8.2.1.6 Anti voltage surge (AVS)
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8.4 Algorithm_Control Registers

ALGORITHM_CONTROL Registers lists the memory-mapped registers for the Algorithm_Control registers. All register offset addresses not listed in ALGORITHM_CONTROL Registers should be considered as reserved locations and the register contents should not be modified.

Table 7-57 ALGORITHM_CONTROL Registers
AddressAcronymRegister NameSection
EChALGO_CTRL1Algorithm Control RegisterALGO_CTRL1 Register (Address = ECh) [Reset = 00000000h]
EEhALGO_CTRL2Algorithm Control RegisterALGO_CTRL2 Register (Address = EEh) [Reset = 00000000h]
F0hCURRENT_PICurrent PI Controller RegisterCURRENT_PI Register (Address = F0h) [Reset = 00000000h]
F2hSPEED_PISpeed PI Controller RegisterSPEED_PI Register (Address = F2h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. Algorithm_Control Access Type Codes shows the codes that are used for access types in this section.

Table 7-58 Algorithm_Control Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.8.4.1 ALGO_CTRL1 Register (Address = ECh) [Reset = 00000000h]

ALGO_CTRL1 is shown in ALGO_CTRL1 Register and described in ALGO_CTRL1 Register Field Descriptions.

Return to the Summary Table.

Algorithm control register for debug

Figure 7-85 ALGO_CTRL1 Register
3130292827262524
OVERRIDEDIGITAL_SPEED_CTRL
W-0hW-0h
2322212019181716
DIGITAL_SPEED_CTRL
W-0h
15141312111098
CLOSED_LOOP_DISFORCE_ALIGN_ENFORCE_SLOW_FIRST_CYCLE_ENFORCE_IPD_ENFORCE_ISD_ENFORCE_ALIGN_ANGLE_SRC_SELFORCE_IQ_REF_SPEED_LOOP_DIS
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
FORCE_IQ_REF_SPEED_LOOP_DIS
W-0h
Table 7-59 ALGO_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
31OVERRIDEW0h Use to control the SPD_CTRL bits. If OVERRIDE = 1b, speed command can be written by the user through serial interface.

0h = SPEED_CMD using Analog/PWM/Freq mode

1h = SPEED_CMD using SPD_CTRL[14:0]

30-16DIGITAL_SPEED_CTRLW0h Digital speed control If OVERRIDE = 1b, then SPEED_CMD is control using DIGITAL_SPEED_CTRL
15CLOSED_LOOP_DISW0h Use to disable closed loop

0h = Enable Closed Loop

1h = Disable Closed loop, motor commutation in open loop

14FORCE_ALIGN_ENW0h Force align state enable

0h = Disable Force Align state, device comes out of align state if MTR_STARTUP is selected as ALIGN or DOUBLE ALIGN

1h = Enable Force Align state, device stays in align state if MTR_STARTUP is selected as ALIGN or DOUBLE ALIGN

13FORCE_SLOW_FIRST_CYCLE_ENW0h Force slow first cycle enable

0h = Disable Force Slow First Cycle state, device comes out of slow first cycle state if MTR_STARTUP is selected as SLOW FIRST CYCLE

1h = Enable Force Slow First Cycle state, device stays in slow first cycle state if MTR_STARTUP is selected as SLOW FIRST CYCLE

12FORCE_IPD_ENW0h Force IPD enable

0h = Disable Force IPD state, device comes out of IPD state if MTR_STARTUP is selected as IPD

1h = Enable Force IPD state, device stays in IPD state if MTR_STARTUP is selected as IPD

11FORCE_ISD_ENW0h Force ISD enable

0h = Disable Force ISD state, device comes out of ISD state if ISD_EN is set

1h = Enable Force ISD state, device stays in ISD state if ISD_EN is set

10FORCE_ALIGN_ANGLE_SRC_SELW0h Force align angle state source select

0h = Force Align Angle defined by ALIGN_ANGLE

1h = Force Align Angle defined by FORCED_ALIGN_ANGLE

9-0FORCE_IQ_REF_SPEED_LOOP_DISW0h Sets Iq_ref when speed loop is disabled If SPEED_LOOP_DIS = 1b, then Iq_ref is set using IQ_REF_SPEED_LOOP_DIS Iq_ref = (FORCE_IQ_REF_SPEED_LOOP_DIS / 500) * 10, if FORCE_IQ_REF_SPEED_LOOP_DIS < 500 -(FORCE_IQ_REF_SPEED_LOOP_DIS - 512) / 500 * 10 if FORCE_IQ_REF_SPEED_LOOP_DIS > 512 Valid values are 0 to 500 and 512 to 1000

7.8.4.2 ALGO_CTRL2 Register (Address = EEh) [Reset = 00000000h]

ALGO_CTRL2 is shown in ALGO_CTRL2 Register and described in ALGO_CTRL2 Register Field Descriptions.

Return to the Summary Table.

Algorithm control register for debug

Figure 7-86 ALGO_CTRL2 Register
3130292827262524
RESERVEDCURRENT_LOOP_DISFORCE_VD_CURRENT_LOOP_DIS
W-0hW-0hW-0h
2322212019181716
FORCE_VD_CURRENT_LOOP_DIS
W-0h
15141312111098
FORCE_VQ_CURRENT_LOOP_DIS
W-0h
76543210
FORCE_VQ_CURRENT_LOOP_DISMPET_CMDMPET_RMPET_LMPET_KEMPET_MECHMPET_WRITE_SHADOW
W-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 7-60 ALGO_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDW0h Reserved
26CURRENT_LOOP_DISW0h Use to control the FORCE_VD_CURRENT_LOOP_DIS and FORCE_VQ_CURRENT_LOOP_DIS. If CURRENT_LOOP_DIS = 1b, current loop and speed loop are disabled

0h = Enable Current Loop

1h = Disable Current Loop

25-16FORCE_VD_CURRENT_LOOP_DISW0h Sets Vd_ref when current loop and speed loop are disabled If CURRENT_LOOP_DIS = 1b, then Vd is controlled using FORCE_VD_CURRENT_LOOP_DIS Vd_ref = (FORCE_VD_CURRENT_LOOP_DIS / 500) if FORCE_VD_CURRENT_LOOP_DIS < 500 -(FORCE_VD_CURRENT_LOOP_DIS - 512) / 500 if FORCE_VD_CURRENT_LOOP_DIS > 512 Valid values: 0 to 500 and 512 to 1000
15-6FORCE_VQ_CURRENT_LOOP_DISW0h Sets Vq_ref when current loop speed loop are disabled If CURRENT_LOOP_DIS = 1b, then Vq is controlled using FORCE_VQ_CURRENT_LOOP_DIS Vq_ref = (FORCE_VQ_CURRENT_LOOP_DIS / 500) if FORCE_VQ_CURRENT_LOOP_DIS < 500 -(FORCE_VQ_CURRENT_LOOP_DIS - 512) / 500 if FORCE_VQ_CURRENT_LOOP_DIS > 512 Valid values: 0 to 500 and 512 to 1000
5MPET_CMDW0h Initiates motor parameter measurement routine when set to 1b
4MPET_RW0h Enables motor resistance measurement during motor parameter measurement routine

0h = Disable Motor Resistance measurement during motor parameter measurement routine

1h = Enable Motor Resistance measurement during motor parameter measurement routine

3MPET_LW0h Enables motor inductance measurement during motor parameter measurement routine

0h = Disable Motor Inductance measurement during motor parameter measurement routine

1h = Enable Motor Inductance measurement during motor parameter measurement routine

2MPET_KEW0h Enables motor BEMF constant measurement during motor parameter measurement routine

0h = Disables Motor BEMF constant measurement during motor parameter measurement routine

1h = Enable Motor BEMF constant measurement during motor parameter measurement routine

1MPET_MECHW0h Enables motor mechanical parameter measurement during motor parameter measurement routine

0h = Disable Motor mechanical parameter measurement during motor parameter measurement routine

1h = Enable Motor mechanical parameter measurement during motor parameter measurement routine

0MPET_WRITE_SHADOWW0h Write measured parameters to shadow register when set to 1b

7.8.4.3 CURRENT_PI Register (Address = F0h) [Reset = 00000000h]

CURRENT_PI is shown in CURRENT_PI Register and described in CURRENT_PI Register Field Descriptions.

Return to the Summary Table.

Current PI controller used

Figure 7-87 CURRENT_PI Register
31302928272625242322212019181716
CURRENT_LOOP_KPCURRENT_LOOP_KI
R-0hR-0h
1514131211109876543210
CURRENT_LOOP_KIRESERVED
R-0hR-0h
Table 7-61 CURRENT_PI Register Field Descriptions
BitFieldTypeResetDescription
31-22CURRENT_LOOP_KPR0h 10-bit value for current loop Kp; same scaling as CURR_LOOP_KP
21-12CURRENT_LOOP_KIR0h 10-bit value for current loop Ki; same scaling as CURR_LOOP_KI
11-0RESERVEDR0h Reserved

7.8.4.4 SPEED_PI Register (Address = F2h) [Reset = 00000000h]

SPEED_PI is shown in SPEED_PI Register and described in SPEED_PI Register Field Descriptions.

Return to the Summary Table.

Speed PI controller used

Figure 7-88 SPEED_PI Register
31302928272625242322212019181716
SPEED_LOOP_KPSPEED_LOOP_KI
R-0hR-0h
1514131211109876543210
SPEED_LOOP_KIRESERVED
R-0hR-0h
Table 7-62 SPEED_PI Register Field Descriptions
BitFieldTypeResetDescription
31-22SPEED_LOOP_KPR0h 10-bit value for speed loo Kp; same scaling as SPD_LOOP_KP
21-12SPEED_LOOP_KIR0h 10-bit value for speed loop Ki; same scaling as SPD_LOOP_KI
11-0RESERVEDR0h Reserved