SLAS701B November   2010  – June 2018 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Resistance Characteristics for PW-24 Package
    5. 5.5  Active Mode Supply Current (Into DVCC and AVCC) Excluding External Current
    6. 5.6  Typical Characteristics – Active-Mode Supply Current (Into DVCC and AVCC)
    7. 5.7  Low-Power-Mode Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Typical Characteristics – LPM4 Current
    9. 5.9  Schmitt-Trigger Inputs (Ports Px and RST/NMI)
    10. 5.10 Leakage Current (Ports Px)
    11. 5.11 Outputs (Ports Px)
    12. 5.12 Output Frequency (Ports Px)
    13. 5.13 Typical Characteristics – Outputs
    14. 5.14 POR, BOR
    15. 5.15 Typical Characteristics – POR, BOR
    16. 5.16 Supply Voltage Supervisor (SVS), Supply Voltage Monitor (SVM)
    17. 5.17 Main DCO Characteristics
    18. 5.18 DCO Frequency
    19. 5.19 Calibrated DCO Frequencies – Tolerance
    20. 5.20 Wake-up Times From Lower-Power Modes (LPM3, LPM4)
    21. 5.21 Typical Characteristics – DCO Clock Wake-up Time
    22. 5.22 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    23. 5.23 Crystal Oscillator (XT2)
    24. 5.24 Typical Characteristics – XT2 Oscillator
    25. 5.25 SD24_A, Power Supply
    26. 5.26 SD24_A, Input Range
    27. 5.27 SD24_A, Performance
    28. 5.28 SD24_A, Temperature Sensor and Built-In VCC Sense
    29. 5.29 SD24_A, Built-In Voltage Reference
    30. 5.30 SD24_A, Reference Output Buffer
    31. 5.31 SD24_A, External Reference Input
    32. 5.32 USART0
    33. 5.33 Timer_A3
    34. 5.34 Flash Memory
    35. 5.35 RAM
    36. 5.36 JTAG and Spy-Bi-Wire Interface
    37. 5.37 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers
      1. Table 6-4 Interrupt Enable Register 1 Field Descriptions
      2. Table 6-5 Interrupt Flag Register 1 Field Descriptions
      3. Table 6-6 Module Enable Register 1 Field Descriptions
    6. 6.6  Memory Organization
    7. 6.7  Flash Memory
    8. 6.8  Peripherals
    9. 6.9  Oscillator and System Clock
    10. 6.10 Brownout, Supply Voltage Supervisor
    11. 6.11 Digital I/O
    12. 6.12 Watchdog Timer (WDT+)
    13. 6.13 Timer_A3
    14. 6.14 USART0
    15. 6.15 Hardware Multiplier
    16. 6.16 SD24_A
    17. 6.17 Peripheral File Map
    18. 6.18 I/O Port Schematics
      1. 6.18.1 Port P1 Pin Schematic: P1.0 Input/Output With Schmitt Trigger
      2. 6.18.2 Port P1 Pin Schematic: P1.1 and P1.2 Input/Output With Schmitt Trigger
      3. 6.18.3 Port P1 Pin Schematic: P1.3 Input/Output With Schmitt Trigger
      4. 6.18.4 Port P1 Pin Schematic: P1.4 Input/Output With Schmitt Trigger
      5. 6.18.5 Port P1 Pin Schematic: P1.5 to P1.7 Input/Output With Schmitt Trigger
      6. 6.18.6 Port P2 Pin Schematic: P2.0 Input/Output With Schmitt Trigger
      7. 6.18.7 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger
      8. 6.18.8 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger
      9. 6.18.9 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Getting Started
    2. 7.2 Device Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Related Links
    6. 7.6 Community Resources
    7. 7.7 Trademarks
    8. 7.8 Electrostatic Discharge Caution
    9. 7.9 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.17 Peripheral File Map

Table 6-10 lists the peripheral registers with word access. Table 6-11 lists the peripheral registers with byte access. Some registers are included in both tables.

Table 6-10 Peripherals With Word Access

PERIPHERAL REGISTER NAME ACRONYM ADDRESS
Timer_A3 Capture/compare register 2 TACCR2 0176h
Capture/compare register 1 TACCR1 0174h
Capture/compare register 0 TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control 2 TACCTL2 0166h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Hardware Multiplier Sum extend SUMEXT 013Eh
Result high word RESHI 013Ch
Result low word RESLO 013Ah
Second operand OP2 0138h
Multiply signed + accumulate/operand 1 MACS 0136h
Multiply + accumulate/operand 1 MAC 0134h
Multiply signed/operand 1 MPYS 0132h
Multiply unsigned/operand 1 MPY 0130h
Flash Memory Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
Watchdog Timer+ Watchdog/timer control WDTCTL 0120h
SD24_A (also see Table 6-11) General Control SD24CTL 0100h
Channel 0 Control SD24CCTL0 0102h
Channel 1Control SD24CCTL1 0104h
Channel 2 Control SD24CCTL2 0106h
Channel 0 conversion memory SD24MEM0 0110h
Channel 1 conversion memory SD24MEM1 0112h
Channel 2 conversion memory SD24MEM2 0114h
SD24 Interrupt vector word register SD24IV 01AEh

Table 6-11 Peripherals With Byte Access

PERIPHERAL REGISTER NAME ACRONYM ADDRESS
SD24_A (also see Table 6-10) Channel 0 Input Control SD24INCTL0 00B0h
Channel 1 Input Control SD24INCTL1 00B1h
Channel 2 Input Control SD24INCTL2 00B2h
Channel 0 Preload SD24PRE0 00B8h
Channel 1 Preload SD24PRE1 00B9h
Channel 2 Preload SD24PRE2 00BAh
Reserved (Internal SD24_A Configuration 1) SD24CONF1 00BFh
USART0 Transmit buffer U0TXBUF 0077h
Receive buffer U0RXBUF 0076h
Baud rate U0BR1 0075h
Baud rate U0BR0 0074h
Modulation control U0MCTL 0073h
Receive control U0RCTL 0072h
Transmit control U0TCTL 0071h
USART control U0CTL 0070h
Basic Clock System+ Basic clock system control 3 BCSCTL3 0053h
Basic clock system control 2 BCSCTL2 0058h
Basic clock system control 1 BCSCTL1 0057h
DCO clock frequency control DCOCTL 0056h
Brownout, SVS SVS control register (reset by brownout signal) SVSCTL 0055h
Port P2 Port P2 selection 2 P2SEL2 0042h
Port P2 resistor enable P2REN 002Fh
Port P2 selection P2SEL 002Eh
Port P2 interrupt enable P2IE 002Dh
Port P2 interrupt edge select P2IES 002Ch
Port P2 interrupt flag P2IFG 002Bh
Port P2 direction P2DIR 002Ah
Port P2 output P2OUT 0029h
Port P2 input P2IN 0028h
Port P1 Port P1 selection 2 register P1SEL2 0041h
Port P1 resistor enable P1REN 0027h
Port P1 selection P1SEL 0026h
Port P1 interrupt enable P1IE 0025h
Port P1 interrupt edge select P1IES 0024h
Port P1 interrupt flag P1IFG 0023h
Port P1 direction P1DIR 0022h
Port P1 output P1OUT 0021h
Port P1 input P1IN 0020h
Special Function SFR module enable 2 ME2 0005h
SFR module enable 1 ME1 0004h
SFR interrupt flag 2 IFG2 0003h
SFR interrupt flag 1 IFG1 0002h
SFR interrupt enable 2 IE2 0001h
SFR interrupt enable 1 IE1 0000h