SLAS421B April   2004  – November 2016 MSP430F423 , MSP430F425 , MSP430F427

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC and DVCC Excluding External Current
    5. 5.5  Thermal Resistance Characteristics, PM Package (LQFP64)
    6. 5.6  Schmitt-Trigger Inputs − Ports (P1 and P2), RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)
    7. 5.7  Inputs P1.x, P2.x, TAx
    8. 5.8  Leakage Current − Ports (P1 and P2)
    9. 5.9  Outputs − Ports (P1 and P2)
    10. 5.10 Output Frequency
    11. 5.11 Typical Characteristics - Ports P1 and P2
    12. 5.12 Wake-up Time From LPM3
    13. 5.13 RAM
    14. 5.14 LCD
    15. 5.15 USART0
    16. 5.16 POR, BOR
    17. 5.17 SVS (Supply Voltage Supervisor and Monitor)
    18. 5.18 DCO
    19. 5.19 Crystal Oscillator, LFXT1 Oscillator
    20. 5.20 SD16 Power Supply and Operating Characteristics
    21. 5.21 SD16 Analog Input Range
    22. 5.22 SD16 Analog Performance
    23. 5.23 SD16 Built-in Temperature Sensor
    24. 5.24 SD16 Built-in Voltage Reference
    25. 5.25 SD16 Built-in Reference Output Buffer
    26. 5.26 SD16 External Reference Input
    27. 5.27 Flash Memory
    28. 5.28 JTAG Interface
    29. 5.29 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  Oscillator and System Clock
      2. 6.9.2  Brownout, Supply Voltage Supervisor (SVS)
      3. 6.9.3  Digital I/O
      4. 6.9.4  Basic Timer1
      5. 6.9.5  LCD Driver
      6. 6.9.6  Watchdog Timer (WDT+)
      7. 6.9.7  Timer_A3
      8. 6.9.8  USART0
      9. 6.9.9  Hardware Multiplier
      10. 6.9.10 SD16
      11. 6.9.11 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      2. 6.10.2 Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      3. 6.10.3 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger
      4. 6.10.4 Port P2 (P2.2 to P2.5) Input/Output With Schmitt Trigger
      5. 6.10.5 Port P2 (P2.6 and P2.7) Unbonded GPIOs
      6. 6.10.6 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt-Trigger or Output
      7. 6.10.7 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1  Getting Started and Next Steps
    2. 7.2  Device Nomenclature
    3. 7.3  Tools and Software
    4. 7.4  Documentation Support
    5. 7.5  Related Links
    6. 7.6  Community Resources
    7. 7.7  Trademarks
    8. 7.8  Electrostatic Discharge Caution
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description

CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers (see Figure 6-1).

Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be manged with all instructions.

MSP430F427 MSP430F425 MSP430F423 cpu_registers.gif Figure 6-1 CPU Registers

Instruction Set

The instruction set consists of the original 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 6-1 lists examples of the three types of instruction formats, and Table 6-2 lists the address modes.

Table 6-1 Instruction Word Formats

INSTRUCTION FORMAT EXAMPLE OPERATION
Dual operands, source and destination ADD R4,R5 R4 + R5 → R5
Single operand, destination only CALL R8 PC→(TOS), R8 →PC
Relative jump, unconditional or conditional JNE Jump-on-equal bit = 0

Table 6-2 Address Mode Descriptions

ADDRESS MODE S(1) D(1) SYNTAX EXAMPLE OPERATION
Register MOV Rs, Rd MOV R10, R11 R10 → R11
Indexed MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) M(2+R5)→ M(6+R6)
Symbolic (PC relative) MOV EDE, TONI M(EDE) → M(TONI)
Absolute MOV & MEM, & TCDAT M(MEM) → M(TCDAT)
Indirect MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) → M(Tab+R6)
Indirect autoincrement MOV @Rn+, Rm MOV @R10+, R11 M(R10) → R11
R10 + 2→ R10
Immediate MOV #X, TONI MOV #45, TONI #45 → M(TONI)
S = source, D = destination

Operating Modes

The MSP430F42x has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

Software can configure the following operating modes:

  • Active mode (AM)
    • All clocks are active.
  • Low-power mode 0 (LPM0)
    • CPU is disabled.
    • ACLK and SMCLK remain active, MCLK available to modules.
    • FLL+ loop control remains active.
  • Low-power mode 1 (LPM1)
    • CPU is disabled.
    • ACLK and SMCLK remain active, MCLK available to modules.
    • FLL+ loop control is disabled.
  • Low-power mode 2 (LPM2)
    • CPU is disabled.
    • MCLK, FLL+ loop control, and DCOCLK are disabled.
    • DC generator of the DCO remains enabled.
    • ACLK remains active.
  • Low-power mode 3 (LPM3)
    • CPU is disabled.
    • MCLK, FLL+ loop control, and DCOCLK are disabled.
    • DC generator of the DCO is disabled.
    • ACLK remains active.
  • Low-power mode 4 (LPM4)
    • CPU is disabled.
    • ACLK is disabled.
    • MCLK, FLL+ loop control, and DCOCLK are disabled.
    • DC generator of the DCO is disabled.
    • Crystal oscillator is stopped.

Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6-3 lists the interrupt sources, flags, and vectors.

Table 6-3 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power up
External reset
Watchdog
Flash memory
PC out of range(4)
WDTIFG
KEYV(1)
Reset 0FFFEh 15, highest
NMI oscillator fault
Flash memory access violation
NMIIFG(1)
OFIFG(1)
ACCVIFG(1)
(Non)maskable(3)
(Non)maskable
(Non)maskable
0FFFCh 14
0FFFAh 13
SD16 SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG(1)(2)
Maskable 0FFF8h 12
0FFF6h 11
Watchdog timer WDTIFG Maskable 0FFF4h 10
USART0 receive URXIFG0 Maskable 0FFF2h 9
USART0 transmit UTXIFG0 Maskable 0FFF0h 8
0FFEEh 7
Timer_A3 TACCR0 CCIFG(2) Maskable 0FFECh 6
Timer_A3 TACCR1 and TACCR2
CCIFGs, and TACTL TAIFG(1)(2)
Maskable 0FFEAh 5
I/O port P1 (8 flags) P1IFG.0 to P1IFG.7(1)(2) Maskable 0FFE8h 4
0FFE6h 3
0FFE4h 2
I/O port P2 (8 flags) P2IFG.0 to P2IFG.7(1)(2) Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
Multiple source flags
Interrupt flags are in the module.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from within unused address ranges (0600h–0BFFh).

Special Function Registers

Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.

Legend
rw Bit can be read and written.
rw-0, rw-1 Bit can be read and written. It is reset or set by PUC.
rw-(0), rw-(1) Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.

Figure 6-2 shows the Interrupt Enable Register 1, and Table 6-4 describes the bit fields.

Figure 6-2 Interrupt Enable Register 1 (Address = 00h)
7 6 5 4 3 2 1 0
UTXIE0 URXIE0 ACCVIE NMIIE OFIE WDTIE
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0

Table 6-4 Interrupt Enable Register 1 Description

BIT FIELD TYPE RESET DESCRIPTION
7 UTXIE0 RW 0h USART0: UART and SPI transmit interrupt enable
6 URXIE0 RW 0h USART0: UART and SPI receive interrupt enable
5 ACCVIE RW 0h Flash access violation interrupt enable
4 NMIIE RW 0h (Non)maskable interrupt enable
1 OFIE RW 0h Oscillator fault interrupt enable
0 WDTIE RW 0h Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode.

Figure 6-3 shows the Interrupt Enable Register 2, and Table 6-5 describes the bit fields.

Figure 6-3 Interrupt Enable Register 2 (Address = 01h)
7 6 5 4 3 2 1 0
BTIE
 rw-0

Table 6-5 Interrupt Enable Register 2 Description

BIT FIELD TYPE RESET DESCRIPTION
7 BTIE RW 0h Basic Timer1 interrupt enable

Figure 6-4 shows the Interrupt Flag Register 1, and Table 6-6 describes the bit fields.

Figure 6-4 Interrupt Flag Register 1 (Address = 02h)
7 6 5 4 3 2 1 0
UTXIFG0 URXIFG0 NMIIFG OFIFG WDTIFG
rw-1 rw-0 rw-0 rw-1 rw-(0)

Table 6-6 Interrupt Flag Register 1 Description

BIT FIELD TYPE RESET DESCRIPTION
7 UTXIFG0 RW 1h USART0: UART and SPI transmit flag
6 URXIFG0 RW 0h USART0: UART and SPI receive flag
4 NMIIFG RW 0h Set by the RST/NMI pin
1 OFIFG RW 1h Flag set on oscillator fault.
0 WDTIFG RW 0h Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power on or a reset condition at the RST/NMI pin in reset mode.

Figure 6-5 shows the Interrupt Flag Register 2, and Table 6-7 describes the bit fields.

Figure 6-5 Interrupt Flag Register 2 (Address = 03h)
7 6 5 4 3 2 1 0
 BTIFG
 rw-0

Table 6-7 Interrupt Flag Register 2 Description

BIT FIELD TYPE RESET DESCRIPTION
7 BTIFG RW 0h Basic Timer1 interrupt flag

Figure 6-6 shows the Module Enable Register 1, and Table 6-8 describes the bit fields.

Figure 6-6 Module Enable Register 1 (Address = 04h)
7 6 5 4 3 2 1 0
UTXE0 URXE0
USPIE0
rw-0 rw-0

Table 6-8 Module Enable Register 1 Description

BIT FIELD TYPE RESET DESCRIPTION
7 UTXE0 RW 0h USART0: UART mode transmit enable
6 URXE0
USPIE0
RW 0h USART0: UART mode receive enable
USART0: SPI mode transmit and receive enable

Module Enable Register 2 is not defined for the MSP430F42x MCUs.

Memory Organization

Table 6-9 summarizes the memory map of the MSP430F42x MCUs.

Table 6-9 Memory Organization

MSP430F423 MSP430F425 MSP430F427
Memory Size 8KB 16KB 32KB
  Interrupt vector Flash 0FFFFh–0FFE0h 0FFFFh–0FFE0h 0FFFFh–0FFE0h
  Code memory Flash 0FFFFh–0E000h 0FFFFh–0C000h 0FFFFh–08000h
  Information memory Size 256 Byte 256 Byte 256 Byte
010FFh–01000h 010FFh–01000h 010FFh–01000h
  Boot memory Size 1KB 1KB 1KB
0FFFh–0C00h 0FFFh–0C00h 0FFFh–0C00h
RAM Size 256 Byte 512 Byte 1KB
02FFh–0200h 03FFh–0200h 05FFh–0200h
Peripherals 16-bit 01FFh–0100h 01FFh–0100h 01FFh–0100h
8-bit 0FFh–010h 0FFh–010h 0FFh–010h
8-bit SFR 0Fh–00h 0Fh–00h 0Fh–00h

Bootloader (BSL)

The BSL lets users program the flash memory or RAM using a UART serial interface. Access to the MCU memory through the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see MSP430 Programming WIth the Bootloader (BSL).

BSL FUNCTION PM PACKAGE PINS
Data transmit 53 - P1.0
Data receiver 52 - P1.1

Flash Memory

The flash memory (see Figure 6-7) can be programmed using the JTAG port, the bootloader, or in system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

  • Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.
  • Segments 0 to n may be erased in one step, or each segment may be individually erased.
  • Segments A and B can be erased individually, or as a group with segments 0 to n. Segments A and B are also called information memory.
  • New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory before the first use.

MSP430F427 MSP430F425 MSP430F423 flash_memory_map.gif Figure 6-7 Flash Memory Map

Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be managed using all instructions. For complete module descriptions, see the MSP430x4xx Family User's Guide.

Oscillator and System Clock

The clock system is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than 6 µs. The FLL+ module provides the following clock signals:

  • Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
  • Main clock (MCLK), the system clock used by the CPU
  • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
  • ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

Brownout, Supply Voltage Supervisor (SVS)

The brownout circuit provides the proper internal reset signal to the device during power on and power off. The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must ensure that the default FLL+ settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).

Digital I/O

Two I/O ports are implemented: ports P1 and P2 (only six P2 I/O signals are available on external pins).

  • All individual I/O bits are independently programmable.
  • Any combination of input, output, and interrupt conditions is possible.
  • Edge-selectable interrupt input capability for all the 8 bits of ports P1 and P2.
  • Read/write access to port-control registers is supported by all instructions.

NOTE

Six bits of port P2 (P2.0 to P2.5) are available on external pins, but all control and data bits for port P2 are implemented.

Basic Timer1

The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and clock for the LCD module.

LCD Driver

The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported by this peripheral.

Watchdog Timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

Timer_A3

Timer_A3 is a 16-bit timer and counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-10). Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-10 Timer_A3 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER
48 - P1.5 TACLK TACLK Timer NA
ACLK ACLK
SMCLK SMCLK
48 - P1.5 TACLK INCLK
53 - P1.0 TA0 CCI0A CCR0 TA0 53 - P1.0
52 - P1.1 TA0 CCI0B
DVSS GND
DVCC VCC
51 - P1.2 TA1 CCI1A CCR1 TA1 51 - P1.2
51 - P1.2 TA1 CCI1B
DVSS GND
DVCC VCC
45 - P2.0 TA2 CCI2A CCR2 TA2 45 - P2.0
ACLK (internal) CCI2B
DVSS GND
DVCC VCC

USART0

The MSP430F42x devices have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. USART0 supports synchronous SPI (3- or 4-pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.

Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs 16- × 16-bit, 16- × 8-bit, 8- × 16-bit, and 8- × 8-bit operations. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.

SD16

The SD16 module integrates three independent 16-bit sigma-delta ADCs, an internal temperature sensor, and a built-in voltage reference. Each channel is designed with a fully differential analog input pair and programmable gain amplifier input stage.

Peripheral File Map

Table 6-11 and Table 6-12 list the peripheral registers with their addresses.

Table 6-11 Peripherals With Word Access

MODULE REGISTER NAME ACRONYM ADDRESS
Watchdog Watchdog timer control WDTCTL 0120h
Timer_A3 Timer0_A interrupt vector TA0IV 012Eh
Timer0_A control TACTL0 0160h
Capture/compare control 0 TACCTL0 0162h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 2 TACCTL2 0166h
Reserved 0168h
Reserved 016Ah
Reserved 016Ch
Reserved 016Eh
Timer_A counter TA0R 0170h
Capture/compare 0 TACCR0 0172h
Capture/compare 1 TACCR1 0174h
Capture/compare 2 TACCR2 0176h
Reserved 0178h
Reserved 017Ah
Reserved 017Ch
Reserved 017Eh
Hardware Multiplier Sum extend SUMEXT 013Eh
Result high word RESHI 013Ch
Result low word RESLO 013Ah
Second operand OP2 0138h
Multiply signed + accumulate/operand 1 MACS 0136h
Multiply + accumulate/operand 1 MAC 0134h
Multiply signed/operand 1 MPYS 0132h
Multiply unsigned/operand 1 MPY 0130h
Flash Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
SD16
(also see Table 6-12)
General control SD16CTL 0100h
Channel 0 control SD16CCTL0 0102h
Channel 1 control SD16CCTL1 0104h
Channel 2 control SD16CCTL2 0106h
Reserved 0108h
Reserved 010Ah
Reserved 010Ch
Reserved 010Eh
Interrupt vector word SD16IV 0110h
Channel 0 conversion memory SD16MEM0 0112h
Channel 1 conversion memory SD16MEM1 0114h
Channel 2 conversion memory SD16MEM2 0116h
Reserved 0118h
Reserved 011Ah
Reserved 011Ch
Reserved 011Eh

Table 6-12 Peripherals With Byte Access

MODULE REGISTER NAME ACRONYM ADDRESS
SD16
(also see Table 6-11)
Channel 0 input control SD16INCTL0 0B0h
Channel 1 input control SD16INCTL1 0B1h
Channel 2 input control SD16INCTL2 0B2h
Reserved 0B3h
Reserved 0B4h
Reserved 0B5h
Reserved 0B6h
Reserved 0B7h
Channel 0 preload SD16PRE0 0B8h
Channel 1 preload SD16PRE1 0B9h
Channel 2 preload SD16PRE2 0BAh
Reserved 0BBh
Reserved 0BCh
Reserved 0BDh
Reserved 0BEh
Reserved 0BFh
LCD LCD memory 20 LCDM20 0A4h
  ⋮   ⋮   ⋮
LCD memory 16 LCDM16 0A0h
LCD memory 15 LCDM15 09Fh
  ⋮   ⋮   ⋮
LCD memory 1 LCDM1 091h
LCD control and mode LCDCTL 090h
USART0 Transmit buffer U0TXBUF 077h
Receive buffer U0RXBUF 076h
Baud rate 1 U0BR1 075h
Baud rate 0 U0BR0 074h
Modulation control U0MCTL 073h
Receive control U0RCTL 072h
Transmit control U0TCTL 071h
USART control U0CTL 070h
Brownout, SVS SVS control register SVSCTL 056h
FLL+ Clock FLL+ control 1 FLL_CTL1 054h
FLL+ control 0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h
Basic Timer1 BT counter 2 BTCNT2 047h
BT counter 1 BTCNT1 046h
BT control BTCTL 040h
Port P2 Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt-edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Functions SFR module enable 2 ME2 005h
SFR module enable 1 ME1 004h
SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h

Input/Output Diagrams

Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger

Figure 6-8 shows the port diagram. Table 6-13 summarizes the selection of the port function.

MSP430F427 MSP430F425 MSP430F423 port_p1_01.gif

NOTE:

0 ≤ x ≤ 1. Port function is active if CAPD.x = 0.
Figure 6-8 Port P1 (P1.0 and P1.1) Diagram

Table 6-13 Port P1 (P1.0 and P1.1) Pin Function

P1SEL.x P1DIR.x DIRECTION CONTROL FROM MODULE P1OUT.x MODULE X OUT P1IN.x MODULE X IN P1IE.x P1IFG.x P1IES.x CAPD.x
P1SEL.0 P1DIR.0 P1DIR.0 P1OUT.0 Out0 Sig.(1) P1IN.0 CCI0A(1) P1IE.0 P1IFG.0 P1IES.0 DVSS
P1SEL.1 P1DIR.1 P1DIR.1 P1OUT.1 MCLK P1IN.1 CCI0B(1) P1IE.1 P1IFG.1 P1IES.1 DVSS
Timer_A3

Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger

Figure 6-9 shows the port diagram. Table 6-14 summarizes the selection of the port function.

MSP430F427 MSP430F425 MSP430F423 port_p1_234567.gif

NOTE:

2 ≤ x ≤ 7. Port function is active if Port/LCD = 0.
Figure 6-9 Port P1 (P1.2 to P1.7) Diagram

Table 6-14 Port P1 (P1.2 to P1.7) Pin Functions

P1SEL.x P1DIR.x DIRECTION CONTROL FROM MODULE P1OUT.x MODULE X OUT P1IN.x MODULE X IN P1IE.x P1IFG.x P1IES.x Port/LCD SEGMENT
P1SEL.2 P1DIR.2 P1DIR.2 P1OUT.2 Out1 Sig.(1) P1IN.2 CCI1A† P1IE.2 P1IFG.2 P1IES.2 0: LCDPx < 05h,
1: LCDPx ≥ 05h
S31
P1SEL.3 P1DIR.3 P1DIR.3 P1OUT.3 SVSOUT P1IN.3 unused P1IE.3 P1IFG.3 P1IES.3 S30
P1SEL.4 P1DIR.4 P1DIR.4 P1OUT.4 DVSS P1IN.4 unused P1IE.4 P1IFG.4 P1IES.4 S29
P1SEL.5 P1DIR.5 P1DIR.5 P1OUT.5 ACLK P1IN.5 TACLK(1) P1IE.5 P1IFG.5 P1IES.5 S28
P1SEL.6 P1DIR.6 DCM_SIMO P1OUT.6 SIMO0(o)(2) P1IN.6 SIMO0(i)(2) P1IE.6 P1IFG.6 P1IES.6 0: LCDPx < 04h,
1: LCDPx ≥ 04h
S27
P1SEL.7 P1DIR.7 DCM_SOMI P1OUT.7 SOMI0(o)(2) P1IN.7 SOMI0(i)(2) P1IE.7 P1IFG.7 P1IES.7 S26
Timer_A3
USART0 (also see Figure 6-10)
MSP430F427 MSP430F425 MSP430F423 port_p1_direction_simo_somi.gif Figure 6-10 Direction Control for SIMO0 and SOMI0

Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger

Figure 6-11 shows the port diagram. Table 6-15 summarizes the selection of the port function.

MSP430F427 MSP430F425 MSP430F423 port_p2_01.gif

NOTE:

0 ≤ x ≤ 1. Port function is active if Port/LCD = 0.
Figure 6-11 Port P2 (P2.0 and P2.1) Diagram

Table 6-15 Port P2 (P2.0 and P2.1) Pin Functions

P2Sel.x P2DIR.x DIRECTION CONTROL FROM MODULE P2OUT.x MODULE X OUT P2IN.x MODULE X IN P2IE.x P2IFG.x P2IES.x Port/LCD SEGMENT
P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 Out2 Sig.(1) P2IN.0 CCI2A(1) P2IE.0 P2IFG.0 P2IES.0 0: LCDPx < 04h,
1: LCDPx ≥ 04h
S25
P2Sel.1 P2DIR.1 DCM_UCLK P2OUT.1 UCLK0(o)(2) P2IN.1 UCLK0(i)(2) P2IE.1 P2IFG.1 P2IES.1 S24
Timer_A3
USART0 (also see Figure 6-12)
MSP430F427 MSP430F425 MSP430F423 port_p2_direction_uclk.gif Figure 6-12 Direction Control for UCLK0

Port P2 (P2.2 to P2.5) Input/Output With Schmitt Trigger

Figure 6-13 shows the port diagram. Table 6-16 summarizes the selection of the port function.

MSP430F427 MSP430F425 MSP430F423 port_p2_2345.gif

NOTE:

2 ≤ x ≤ 5. Port function is active if CAPD.x = 0
Figure 6-13 Port P2 (P2.2 to P2.5) Diagram

Table 6-16 Port P2 (P2.2 to P2.5) Pin Functions

P2SEL.x P2DIR.x DIRECTION CONTROL FROM MODULE P2OUT.x MODULE X OUT P2IN.x MODULE X IN P2IE.x P2IFG.x P2IES.x CAPD.x
P2SEL.2 P2DIR.2 DVSS P2OUT.2 DVSS P2IN.2 STE0(1) P2IE.2 P2IFG.2 P2IES.2 DVSS
P2SEL.3 P2DIR.3 P2DIR.3 P2OUT.3 DVSS P2IN.3 Unused P2IE.3 P2IFG.3 P2IES.3 SVSCTL VLD = 1111b
P2SEL.4 P2DIR.4 DVCC P2OUT.4 UTXD0(1) P2IN.4 Unused P2IE.4 P2IFG.4 P2IES.4 DVSS
P2SEL.5 P2DIR.5 DVSS P2OUT.5 DVSS P2IN.5 URXD0(1) P2IE.5 P2IFG.5 P2IES.5 DVSS
USART0

Port P2 (P2.6 and P2.7) Unbonded GPIOs

Unbonded GPIOs P2.6 and P2.7 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software interrupts.

Figure 6-14 shows the port diagram. Table 6-17 summarizes the selection of the port function.

MSP430F427 MSP430F425 MSP430F423 port_p2_67.gif

NOTE:

x = Bit identifier 6 or 7 for Port P2 without external pins
Figure 6-14 Port P2 (P2.6 and P2.7) Diagram

Table 6-17 Port P2 (P2.6 and P2.7) Pin Functions

P2SEL.x P2DIR.x DIRECTION CONTROL FROM MODULE P2OUT.x MODULE X OUT P2IN.x MODULE X IN P2IE.x P2IFG.x P2IES.x
P2SEL.6 P2DIR.6 P2DIR.6 P2OUT.6 DVSS P2IN.6 Unused P2IE.6 P2IFG.6 P2IES.6
P2SEL.7 P2DIR.7 P2DIR.7 P2OUT.7 DVSS P2IN.7 Unused P2IE.7 P2IFG.7 P2IES.7

JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt-Trigger or Output

Figure 6-15 shows the port diagram.

MSP430F427 MSP430F425 MSP430F423 port_jtag.gif Figure 6-15 JTAG Pins Diagram

JTAG Fuse Check Mode

MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I(TF)) of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Take care to avoid accidentally activating the fuse check mode and increasing overall system power consumption.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated.

The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see Figure 6-16). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and therefore do not require external termination.

MSP430F427 MSP430F425 MSP430F423 fuse_check_current.gif Figure 6-16 Fuse Check Mode Current