SLAS731D December   2011  – September 2018

PRODUCTION DATA.

1. 1Device Overview
2. 2Revision History
3. 3Device Comparison
4. 4Terminal Configuration and Functions
1. 4.1 Pin Diagrams
2. 4.2 Signal Descriptions
5. 5Specifications
6. 6Detailed Description
7. 7Device and Documentation Support
8. 8Mechanical, Packaging, and Orderable Information

• PN|80
• PZ|100

### Table 5-36 SD24_B Power Supply and Recommended Operating Conditions

MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC = DVCC, AVSS = DVSS = 0 V 2.4 3.6 V
fSD Modulator clock frequency(1) 0.03 2.3 MHz
VI Absolute input voltage range AVSS – 1 AVCC V
VIC Common-mode input voltage range AVSS – 1 AVCC V
VID,FS Differential full-scale input voltage VID = VI,A+ – VI,A– –VREF/GAIN +VREF/GAIN mV
VID Differential input voltage for specified performance(2) SD24REFS = 1 SD24GAINx = 1 ±910 ±920
SD24GAINx = 2 ±455 ±460
SD24GAINx = 4 ±227 ±230
SD24GAINx = 8 ±113 ±115
SD24GAINx = 16 ±57 ±58
SD24GAINx = 32 ±28 ±29
SD24GAINx = 64 ±14 ±14.5
SD24GAINx = 128 ±7 ±7.2
CREF VREF load capacitance(3) SD24REFS = 1 100 nF
Modulator clock frequency: MIN = 32.768 kHz – 10% ≈ 30 kHz. MAX = 32.768 kHz × 64 + 10% ≈ 2.3 MHz
The full-scale range (FSR) is defined by VFS+ = +VREF/GAIN and VFS– = –VREF/GAIN: FSR = VFS+ – VFS– = 2 × VREF / GAIN. If VREF is sourced externally, the analog input range should not exceed 80% of VFS+ or VFS–; that is, VID = 0.8 VFS– to 0.8 VFS+. If VREF is sourced internally, the given VID ranges apply.
There is no capacitance required on VREF. However, a capacitance of 100 nF is recommended to reduce any reference voltage noise.