SLAS380F April   2004  – March 2022 MSP430FG437 , MSP430FG438 , MSP430FG439

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  Handling Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Supply Current Into AVCC + DVCC Excluding External Current
    5. 8.5  Schmitt-Trigger Inputs – Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
    6. 8.6  Inputs Px.y, TAx, TBx
    7. 8.7  Leakage Current – Ports P1 to P6
    8. 8.8  Outputs – Ports P1 to P6
    9. 8.9  Output Frequency
    10. 8.10 Typical Characteristics – Outputs
    11. 8.11 Wake-Up From LPM3
    12. 8.12 RAM
    13. 8.13 LCD
    14. 8.14 Comparator_A
    15. 8.15 Comparator_A Typical Characteristics
    16. 8.16 Power-On Reset (POR) and Brownout Reset (BOR)
    17. 8.17 Supply Voltage Supervisor (SVS) and Supply Voltage Monitor (SVM)
    18. 8.18 DCO
    19. 8.19 Crystal Oscillator, XT1 Oscillator
    20. 8.20 Crystal Oscillator, XT2 Oscillator
    21. 8.21 USART0
    22. 8.22 12-Bit ADC, Power Supply and Input Range Conditions
    23. 8.23 12-Bit ADC, External Reference
    24. 8.24 12-Bit ADC, Built-In Reference
    25. 8.25 12-Bit ADC, Timing Parameters
    26. 8.26 12-Bit ADC, Linearity Parameters
    27. 8.27 12-Bit ADC, Temperature Sensor and Built-In VMID
    28. 8.28 12-Bit DAC, Supply Specifications
    29. 8.29 12-Bit DAC, Linearity Specifications
    30. 8.30 12-Bit DAC, Output Specifications
    31. 8.31 12-Bit DAC, Reference Input Specifications
    32. 8.32 12-Bit DAC, Dynamic Specifications
    33. 8.33 12-Bit DAC, Dynamic Specifications (Continued)
    34. 8.34 Operational Amplifier (OA), Supply Specifications
    35. 8.35 Operational Amplifier (OA), Input/Output Specifications
    36. 8.36 Operational Amplifier (OA), Dynamic Specifications
    37. 8.37 OA Dynamic Specifications Typical Characteristics
    38. 8.38 Flash Memory
    39. 8.39 JTAG Interface
    40. 8.40 JTAG Fuse
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Instruction Set
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Special Function Registers (SFRs)
      1. 9.5.1 Interrupt Enable Registers 1 and 2
      2. 9.5.2 Interrupt Flag Registers 1 and 2
      3. 9.5.3 Module Enable Registers 1 and 2
    6. 9.6  Memory Organization
    7. 9.7  Bootstrap Loader (BSL)
    8. 9.8  Flash Memory
    9. 9.9  Peripherals
      1. 9.9.1  DMA Controller
      2. 9.9.2  Oscillator and System Clock
      3. 9.9.3  Brownout, Supply Voltage Supervisor
      4. 9.9.4  Digital I/O
      5. 9.9.5  Basic Timer1
      6. 9.9.6  LCD Drive
      7. 9.9.7  OA
      8. 9.9.8  Watchdog Timer (WDT)
      9. 9.9.9  USART0
      10. 9.9.10 Timer_A3
      11. 9.9.11 Timer_B3
      12. 9.9.12 Comparator_A
      13. 9.9.13 ADC12
      14. 9.9.14 DAC12
      15. 9.9.15 Peripheral File Map
    10. 9.10 Input/Output Schematics
      1. 9.10.1  Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
      2. 9.10.2  Port P1, P1.6 and P1.7, Input/Output With Schmitt Trigger
      3. 9.10.3  Port P2, P2.0 and P2.4 to P2.5, Input/Output With Schmitt Trigger
      4. 9.10.4  Port P2, P2.1 to P2.3, Input/Output With Schmitt Trigger
      5. 9.10.5  Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
      6. 9.10.6  Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
      7. 9.10.7  Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      8. 9.10.8  Port P4, P4.0 to P4.5, Input/Output With Schmitt Trigger
      9. 9.10.9  Port P4, P4.6, Input/Output With Schmitt Trigger
      10. 9.10.10 Port P4, P4.7, Input/Output With Schmitt Trigger
      11. 9.10.11 Port P5, P5.0, Input/Output With Schmitt Trigger
      12. 9.10.12 Port P5, P5.1, Input/Output With Schmitt Trigger
      13. 9.10.13 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
      14. 9.10.14 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
      15. 9.10.15 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
      16. 9.10.16 Port P6, P6.1, Input/Output With Schmitt Trigger
      17. 9.10.17 Port P6, P6.3, Input/Output With Schmitt Trigger
      18. 9.10.18 Port P6, P6.5, Input/Output With Schmitt Trigger
      19. 9.10.19 Port P6, P6.6, Input/Output With Schmitt Trigger
      20. 9.10.20 Port P6, P6.7, Input/Output With Schmitt Trigger
      21. 9.10.21 VeREF+/DAC0
      22. 9.10.22 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      23. 9.10.23 JTAG Fuse Check Mode
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Development Kit
      2. 10.1.2 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.1 Signal Descriptions

TERMINALI/ODESCRIPTION
NAMENO.
PNZCA
DVCC11B1, C2Digital supply voltage, positive terminal.
P6.3/A3/OA1I1/OA1O2B5I/OGeneral-purpose digital I/O
Analog input a3—12-bit ADC
OA1 output and/or input multiplexer on +terminal and −terminal
P6.4/A4/OA1I03D5I/OGeneral-purpose digital I/O
Analog input a4—12-bit ADC
OA1 input multiplexer on +terminal and −terminal
P6.5/A5/OA2I1/OA2O4D4I/OGeneral-purpose digital I/O
Analog input a5—12-bit ADC
OA2 output and/or input multiplexer on +terminal and −terminal
P6.6/A6/DAC0/OA2I05E4I/OGeneral-purpose digital I/O
Analog input a6—12-bit ADC
DAC12.0 output
OA2 input multiplexer on +terminal and −terminal
P6.7/A7/DAC1/SVSIN6D2I/OGeneral-purpose digital I/O
Analog input a7—12-bit ADC
DAC12.1 output/analog input to supply voltage supervisor
VREF+7C1OPositive output terminal of the reference voltage in the ADC
XIN8E1IInput terminal of crystal oscillator XT1
XOUT9F1OOutput terminal of crystal oscillator XT1
VeREF+/DAC010H1I/OPositive input terminal for an external reference voltage to the 12-bit ADC/DAC12.0 output
VREF−/VeREF−11J1INegative terminal for the 12-bit ADC's reference voltage for both sources, the internal reference voltage or an external applied reference voltage to the 12-bit ADC.
P5.1/S0/A12/DAC112F4I/OGeneral-purpose digital I/O
LCD segment output 0
Analog input a12—12-bit ADC
DAC12.1 output
P5.0/S1/A1313G4I/OGeneral-purpose digital I/O
LCD segment output 1
Analog input a13—12-bit ADC
P4.7/S2/A1414H4I/OGeneral-purpose digital I/O
LCD segment output 2
Analog input a14—12-bit ADC
P4.6/S3/A1515J4I/OGeneral-purpose digital I/O
LCD segment output 3
Analog input a15—12-bit ADC
P4.5/S416K1I/OGeneral-purpose digital I/O
LCD segment output 4
P4.4/S517K2I/OGeneral-purpose digital I/O
LCD segment output 5
P4.3/S618L3I/OGeneral-purpose digital I/O
LCD segment output 6
P4.2/S719L2I/OGeneral-purpose digital I/O
LCD segment output 7
P4.1/S820L1I/OGeneral-purpose digital I/O
LCD segment output 8
P4.0/S921M2I/OGeneral-purpose digital I/O
LCD segment output 9
S1022M3OLCD segment output 10
S1123L4OLCD segment output 11
S1224M4OLCD segment output 12
S1325J5OLCD segment output 13
S1426L5OLCD segment output 14
S1527M5OLCD segment output 15
S1628J6OLCD segment output 16
S1729L6OLCD segment output 17
P2.7/ADC12CLK/S1830M6I/OGeneral-purpose digital I/O
Conversion clock—12-bit ADC
LCD segment output 18
P2.6/CAOUT/S1931M7I/OGeneral-purpose digital I/O
Comparator_A output / LCD segment output 19
S2032L7OLCD segment output 20
S2133J7OLCD segment output 21
S2234J8OLCD segment output 22
S2335J9OLCD segment output 23
P3.7/S2436M8I/OGeneral-purpose digital I/O
LCD segment output 24
P3.6/S25/DMAE037L8I/OGeneral-purpose digital I/O
LCD segment output 25/DMA Channel 0 external trigger
P3.5/S2638L9I/OGeneral-purpose digital I/O
LCD segment output 26
P3.4/S2739L10I/OGeneral-purpose digital I/O
LCD segment output 27
P3.3/UCLK0/S2840M9I/OGeneral-purpose digital I/O
External clock input—USART0/UART or SPI mode, clock output—USART0/SPI mode
LCD segment output 28
P3.2/SOMI0/S2941M10I/OGeneral-purpose digital I/O
Slave out/master in of USART0/SPI mode
LCD segment output 29
P3.1/SIMO0/S3042M11I/OGeneral-purpose digital I/O
Slave in/master out of USART0/SPI mode
LCD segment output 30
P3.0/STE0/S3143L12I/OGeneral-purpose digital I/O
Slave transmit enable-USART0/SPI mode
LCD segment output 31
COM044K11OCommon output, COM0−3 are used for LCD backplanes.
P5.2/COM145J11I/OGeneral-purpose digital I/O
Common output, COM0−3 are used for LCD backplanes.
P5.3/COM246H11I/OGeneral-purpose digital I/O
Common output, COM0−3 are used for LCD backplanes.
P5.4/COM347G11I/OGeneral-purpose digital I/O
Common output, COM0−3 are used for LCD backplanes.
R0348K12IInput port of fourth positive (lowest) analog LCD level (V5)
P5.5/R1349J12I/OGeneral-purpose digital I/O
input port of third most positive analog LCD level (V4 or V3)
P5.6/R2350H12I/OGeneral-purpose digital I/O
Input port of second most positive analog LCD level (V2)
P5.7/R3351G12I/OGeneral-purpose digital I/O
Output port of most positive analog LCD level (V1)
DVCC252F12Digital supply voltage, positive terminal
DVSS253E12Digital supply voltage, negative terminal
P2.5/URXD054D12I/OGeneral-purpose digital I/O
Receive data in—USART0/UART mode
P2.4/UTXD055C12I/OGeneral-purpose digital I/O
Transmit data out—USART0/UART mode
P2.3/TB256F11I/OGeneral-purpose digital I/O
Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB157E11I/OGeneral-purpose digital I/O
Timer_B3 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB058D11I/OGeneral-purpose digital I/O
Timer_B3 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA259C11I/OGeneral-purpose digital I/O
Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA160B12I/OGeneral-purpose digital I/O
Comparator_A input
P1.6/CA061A11I/OGeneral-purpose digital I/O
Comparator_A input
P1.5/TACLK/ACLK62B10I/OGeneral-purpose digital I/O
Timer_A, clock signal TACLK input
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/SMCLK63E9I/OGeneral-purpose digital I/O
Input clock TBCLK—Timer_B3
Submain system clock SMCLK output
P1.3/TBOUTH/SVSOUT64A10I/OGeneral-purpose digital I/O
Switch all PWM digital output ports to high impedance—Timer_B3 TB0 to TB2
SVS: output of SVS comparator
P1.2/TA165B9I/OGeneral-purpose digital I/O
Timer_A, Capture: CCI1A, compare: Out1 output
P1.1/TA0/MCLK66D9I/OGeneral-purpose digital I/O
Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an input on this pin
BSL receive
P1.0/TA067D8I/OGeneral-purpose digital I/O
Timer_A. Capture: CCI0A input, compare: Out0 output
BSL transmit
XT2OUT68A8OOutput terminal of crystal oscillator XT2
XT2IN69A7IInput port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI70D7I/OTest data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK71E7ITest data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS72D6ITest mode select. TMS is used as an input port for device programming and test.
TCK73E6ITest clock. TCK is the clock input port for device programming and test.
RST/NMI74A6IReset or nonmaskable interrupt input
P6.0/A0/OA0I075A5I/OGeneral-purpose digital I/O
Analog input a0 − 12-bit ADC
OA0 input multiplexer on +terminal and −terminal
P6.1/A1/OA0O76A4I/OGeneral-purpose digital I/O
Analog input a1 − 12-bit ADC
OA0 output
P6.2/A2/OA0I177B4I/OGeneral-purpose digital I/O
Analog input a2 − 12-bit ADC
OA0 input multiplexer on + terminal and − terminal
AVSS78A2, D1, E2, F2, G2, G1, H2, J2Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1, and LCD resistive divider circuitry.
DVSS179A1, B2, C3, B6, B7, B8, A9Digital supply voltage, negative terminal
AVCC80A3, B3Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1, and LCD resistive divider circuitry; must not power up prior to DVCC1/DVCC2.
Reserved (1)Reserved
(1) A12, B11, E5, E8, F5, F8, F9, G5, G8, G9, H5, H6, H7, H8, H9, L11, M1, M12 are reserved and should be connected to ground.