SLASEO5C March   2019  – February 2020 MSP430FR2672 , MSP430FR2673 , MSP430FR2675 , MSP430FR2676

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1       Absolute Maximum Ratings
    2. 5.2       ESD Ratings
    3. 5.3       Recommended Operating Conditions
    4. 5.4       Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5       Active Mode Supply Current Per MHz
    6. 5.6       Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7       Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8       Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9       Typical Characteristics – Low-Power Mode Supply Currents
    10. Table 5-1 Typical Characteristics – Current Consumption Per Module
    11. 5.10      Thermal Resistance Characteristics
    12. 5.11      Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. Table 5-2 PMM, SVS and BOR
      2. 5.11.2  Reset Timing
        1. Table 5-3 Wake-up Times From Low-Power Modes and Reset
      3. 5.11.3  Clock Specifications
        1. Table 5-4 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-5 DCO FLL, Frequency
        3. Table 5-6 DCO Frequency
        4. Table 5-7 REFO
        5. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-9 Module Oscillator (MODOSC)
      4. 5.11.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.11.4.1   Typical Characteristics – Outputs at 3 V and 2 V
      5. 5.11.5  Internal Shared Reference
        1. Table 5-12 Internal Shared Reference
      6. 5.11.6  Timer_A and Timer_B
        1. Table 5-13 Timer_A
        2. Table 5-14 Timer_B
      7. 5.11.7  eUSCI
        1. Table 5-15 eUSCI (UART Mode) Clock Frequency
        2. Table 5-16 eUSCI (UART Mode)
        3. Table 5-17 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-18 eUSCI (SPI Master Mode)
        5. Table 5-19 eUSCI (SPI Slave Mode)
        6. Table 5-20 eUSCI (I2C Mode)
      8. 5.11.8  ADC
        1. Table 5-21 ADC, Power Supply and Input Range Conditions
        2. Table 5-22 ADC, Timing Parameters
        3. Table 5-23 ADC, Linearity Parameters
      9. 5.11.9  Enhanced Comparator (eCOMP)
        1. Table 5-24 eCOMP0
      10. 5.11.10 CapTIvate
        1. Table 5-25 CapTIvate Electrical Characteristics
        2. Table 5-26 CapTIvate Signal-to-Noise Ratio Characteristics
      11. 5.11.11 FRAM
        1. Table 5-27 FRAM
      12. 5.11.12 Debug and Emulation
        1. Table 5-28 JTAG, 4-Wire and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Standard Interface
    7. 6.7  Spy-Bi-Wire Interface (SBW)
    8. 6.8  FRAM
    9. 6.9  Memory Protection
    10. 6.10 Peripherals
      1. 6.10.1  Power-Management Module (PMM)
      2. 6.10.2  Clock System (CS) and Clock Distribution
      3. 6.10.3  General-Purpose Input/Output Port (I/O)
      4. 6.10.4  Watchdog Timer (WDT)
      5. 6.10.5  System (SYS) Module
      6. 6.10.6  Cyclic Redundancy Check (CRC)
      7. 6.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.10.8  Timers (TA0, TA1, TA2, TA3 and TB0)
      9. 6.10.9  Hardware Multiplier (MPY)
      10. 6.10.10 Backup Memory (BAKMEM)
      11. 6.10.11 Real-Time Clock (RTC)
      12. 6.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 6.10.13 eCOMP0
      14. 6.10.14 CapTIvate Technology
      15. 6.10.15 Embedded Emulation Module (EEM)
    11. 6.11 Input/Output Diagrams
      1. 6.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.11.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.11.5 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      6. 6.11.6 Port P6 (P6.0 to P6.2) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors
    13. 6.13 Memory
      1. 6.13.1 Memory Organization
      2. 6.13.2 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
      2. 7.2.2 CapTIvate Peripheral
        1. 7.2.2.1 Device Connection and Layout Fundamentals
        2. 7.2.2.2 Measurements
          1. 7.2.2.2.1 SNR
          2. 7.2.2.2.2 Sensitivity
          3. 7.2.2.2.3 Power
    3. 7.3 CapTIvate Technology Evaluation
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Support Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Attributes

Table 4-1 lists the attributes of all pins.

Table 4-1 Pin Attributes

PIN NUMBER SIGNAL NAME(1)(4) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE(5) RESET STATE AFTER BOR(6)
PT RHA RHB
1 1 32 DVCC P Power DVCC N/A
2 2 1 RST (RD) I LVCMOS DVCC PU
NMI I LVCMOS DVCC
SBWTDIO I/O LVCMOS DVCC
3 3 2 TEST (RD) I LVCMOS DVCC PD
SBWTCK I LVCMOS DVCC
4 4 3 P1.4 (RD) I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC
UCA0SIMO I/O LVCMOS DVCC
TA1.2 I/O LVCMOS DVCC
TCK I LVCMOS DVCC
A4 I Analog DVCC
VREF+ O Power DVCC
5 5 4 P1.5 (RD) I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC
UCA0SOMI I/O LVCMOS DVCC
TA1.1 I/O LVCMOS DVCC
TMS I LVCMOS DVCC
A5 I Analog DVCC
6 6 5 P1.6 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC
TA1CLK I LVCMOS DVCC
TDI I LVCMOS DVCC
TCLK I LVCMOS DVCC
A6 I Analog DVCC
7 7 6 P1.7 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC
SMCLK O LVCMOS DVCC
TDO O LVCMOS DVCC
A7 I Analog DVCC
8 8 P4.3 (RD) I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC
UCB1SCL I/O LVCMOS DVCC
TB0.5 I/O LVCMOS DVCC
A8 I Analog DVCC
9 9 P4.4 (RD) I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC
UCB1SDA I/O LVCMOS DVCC
TB0.6 I/O LVCMOS DVCC
A9 I Analog DVCC
10 P5.3 (RD) I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC
TA3.0 I/O LVCMOS DVCC
A10 I Analog DVCC
11 P5.4 (RD) I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC
TA3CLK I/O LVCMOS DVCC
A11 I Analog DVCC
12 10 7 P1.0 (RD) I/O LVCMOS DVCC OFF
UCB0STE I/O LVCMOS DVCC
TA0CLK I LVCMOS DVCC
A0 I Analog DVCC
Veref+ I Power DVCC
13 11 8 P1.1 (RD) I/O LVCMOS DVCC OFF
UCB0CLK I/O LVCMOS DVCC
TA0.1 I/O LVCMOS DVCC
A1 I Analog DVCC
COMP0.0 I Analog DVCC
14 12 9 P1.2 (RD) I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC
UCB0SDA I/O LVCMOS DVCC
TA0.2 I/O LVCMOS DVCC
A2 I Analog DVCC
Veref- I Power DVCC
15 13 10 P1.3 (RD) I/O LVCMOS DVCC OFF
UCB0SOMI I/O LVCMOS DVCC
UCB0SCL I/O LVCMOS DVCC
MCLK O LVCMOS DVCC
A3 I Analog DVCC
16 14 11 P2.2 (RD) I/O LVCMOS DVCC OFF
SYNC I LVCMOS DVCC
ACLK O LVCMOS DVCC
COMP0.1 I Analog DVCC
17 15 P4.5 (RD) I/O LVCMOS DVCC OFF
UCB0SOMI I/O LVCMOS DVCC
UCB0SCL I/O LVCMOS DVCC
TA3.2 I/O LVCMOS DVCC
18 16 P4.6 (RD) I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC
UCB0SDA I/O LVCMOS DVCC
TA3.1 I/O LVCMOS DVCC
19 P5.5 (RD) I/O LVCMOS DVCC OFF
UCB0CLK I/O LVCMOS DVCC
TA2CLK I/O LVCMOS DVCC
20 P5.6 (RD) I/O LVCMOS DVCC OFF
UCB0STE I/O LVCMOS DVCC
TA2.0 I/O LVCMOS DVCC
21 P5.7 (RD) I/O LVCMOS DVCC OFF
TA2.1 I/O LVCMOS DVCC
COMP0.2 I Analog DVCC
22 P6.0 (RD) I/O LVCMOS DVCC OFF
TA2.2 I/O LVCMOS DVCC
COMP0.3 I Analog DVCC
23 17 12 P3.0 (RD) I/O LVCMOS DVCC OFF
TA2.2 I/O LVCMOS DVCC
CAP0.0 I/O Analog VREG
24 18 13 P3.3 (RD) I/O LVCMOS DVCC OFF
TA2.1 I/O LVCMOS DVCC
CAP0.1 I/O Analog VREG OFF
25 19 14 P2.3 (RD) I/O LVCMOS DVCC OFF
TA2.0 I/O LVCMOS DVCC
CAP0.2 I/O Analog VREG
26 20 15 P3.4 (RD) I/O LVCMOS DVCC OFF
TA2CLK I/O LVCMOS DVCC
COMP0OUT O LVCMOS DVCC
CAP0.3 I/O Analog VREG OFF
27 21 16 P3.1 (RD) I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC
CAP1.0 I/O Analog VREG
28 22 17 P2.4 (RD) I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC
CAP1.1 I/O Analog VREG
29 23 18 P2.5 (RD) I/O LVCMOS DVCC OFF
UCA1RXD I LVCMOS DVCC
UCA1SOMI I/O LVCMOS DVCC
CAP1.2 I/O Analog VREG
30 24 19 P2.6 (RD) I/O LVCMOS DVCC OFF
UCA1TXD O LVCMOS DVCC
UCA1SIMO I/O LVCMOS DVCC
CAP1.3 I/O Analog VREG
31 25 20 VREG P Power VREG N/A
32 26 21 P3.7 (RD) I/O LVCMOS DVCC OFF
TA3.2 I/O LVCMOS DVCC
CAP2.0 I/O Analog VREG OFF
33 27 22 P4.0 (RD) I/O LVCMOS DVCC OFF
TA3.1 I/O LVCMOS DVCC
CAP2.1 I/O Analog VREG OFF
34 28 23 P4.1 (RD) I/O LVCMOS DVCC OFF
TA3.0 I/O LVCMOS DVCC
CAP2.2 I/O Analog VREG OFF
35 29 24 P4.2 (RD) I/O LVCMOS DVCC OFF
TA3CLK I/O LVCMOS DVCC
CAP2.3 I/O Analog VREG OFF
36 30 25 P2.7 (RD) I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC
CAP3.0 I/O Analog VREG
37 31 26 P3.5 (RD) I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC
TB0TRG I LVCMOS DVCC
CAP3.1 I/O Analog VREG OFF
38 32 27 P3.2 (RD) I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC
UCB1SDA I/O LVCMOS DVCC
CAP3.2 I/O Analog VREG
39 33 28 P3.6(RD) I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC
UCB1SCL I/O LVCMOS DVCC
CAP3.3 I/O Analog VREG OFF
40 P6.1 (RD) I/O LVCMOS DVCC OFF
TB0CLK I/O LVCMOS DVCC
41 P6.2 (RD) I/O LVCMOS DVCC OFF
TB0.0 I/O LVCMOS DVCC
42 34 P4.7 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC
TB0.1 I/O LVCMOS DVCC
43 35 P5.0 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC
TB0.2 I LVCMOS DVCC
44 36 P5.1 (RD) I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC
UCA0SOMI I/O LVCMOS DVCC
TB0.3 I/O LVCMOS DVCC
45 37 P5.2 (RD) I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC
UCA0SIMO I/O LVCMOS DVCC
TB0.4 I/O LVCMOS DVCC
46 38 29 P2.0 (RD) I/O LVCMOS DVCC OFF
XOUT O LVCMOS DVCC
47 39 30 P2.1 (RD) I/O LVCMOS DVCC OFF
XIN I LVCMOS DVCC
48 40 31 DVSS P Power DVCC N/A
Signals names with (RD) denote the reset default pin name.
Signal types: I = input, O = output, I/O = input or output
Buffer types: LVCMOS, Analog, or Power (see Table 4-3)
To determine the pin mux encodings for each pin, see Section 6.11.
The power source shown in this table is the I/O power source, which may differ from the module power source.
Reset States:
OFF = High impedance with Schmitt trigger and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable