SLAS704G October 2012 – August 2018 MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. Features of the FRAM include:
For MCLK frequencies > 8 MHz, wait states must be configured following the flow described in the Wait State Control section of the FRAM Controller (FRCTRL) chapter in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
For important software design information regarding FRAM including but not limited to partitioning the memory layout according to application-specific code, constant, and data space requirements, the use of FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to maximize application robustness by protecting the program code against unintended write accesses, see MSP430™ FRAM Technology – How To and Best Practices.