SLASEC9 Data sheet

SLASEC9 April 2017 MSP430FR5989-EP

PRODUCTION DATA.

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5 Detailed Description

5.1 Overview

The TI MSP430FR5989-EP families of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals. The architecture, combined with seven low-power modes, is optimized to achieve extended battery life for example in flow metering applications. The devices features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The MSP430FR5989-EP device is a microcontroller configuration with an extended scan interface (ESI) for background water, heat and gas volume metering together with up to five 16-bit timers, a comparator, eUSCIs that support UART, SPI, and I²C, a hardware multiplier, an AES accelerator, DMA, an RTC module with alarm capabilities, up to 83 I/O pins, and a high-performance 12-bit ADC.

5.2 CPU

The MSP430FR5989-EP CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managed with all instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.

5.3 Operating Modes

The MSP430FR5989-EP devices have one active mode and seven software selectable low-power modes of operation (see Table 5-1). An interrupt event can wake up the device from a low-power mode (LPM0 to LPM4), service the request, and restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.

Table 5-1 Operating Modes

MODE	AM		LPM0	LPM1	LPM2	LPM3	LPM4	LPM3.5	LPM4.5
	ACTIVE	ACTIVE, FRAM OFF ⁽¹⁾	CPU OFF ⁽²⁾	CPU OFF	STANDBY	STANDBY	OFF	RTC ONLY	SHUTDOWN WITH SVS	SHUTDOWN WITHOUT SVS
Maximum system clock	16 MHz		16 MHz	16 MHz	50 kHz	50 kHz	0 ⁽³⁾	50 kHz	0 ⁽³⁾
Typical current consumption, T_J = 25°C	103 µA/MHz	65 µA/MHz	75 µA at 1 MHz	40 µA at 1 MHz	0.9 µA	0.4 µA	0.3 µA	0.35 µA	0.2 µA	0.02 µA
Typical wake-up time	N/A		instant.	6 µs	6 µs	7 µs	7 µs	250 µs	250 µs	1000 µs
Wake-up events	N/A		all	all	LF I/O Comp	LF I/O Comp	_ I/O Comp	RTC I/O	_ I/O
CPU	on		off	off	off	off	off	reset	reset
FRAM	on	off⁽¹⁾	standby (or off ⁽¹⁾)	off	off	off	off	off	off
High-frequency peripherals⁽⁶⁾	available		available	available	off	off	off	reset	reset
Low-frequency peripherals⁽⁶⁾	available		available	available	available	available ⁽⁵⁾	off	RTC	reset
Unclocked peripherals⁽⁶⁾	available		available	available	available	available ⁽⁵⁾	available ⁽⁵⁾	reset	reset
MCLK	on (16MHz_MAX)		off	off	off	off	off	off	off
SMCLK	opt. ⁽⁴⁾ (16MHz_MAX)		opt. ⁽⁴⁾ (16MHz_MAX)	opt. ⁽⁴⁾ (16MHz_MAX)	off	off	off	off	off
ACLK	on (50 kHz_MAX)		on (50 kHz_MAX)	on (50 kHz_MAX)	on (50 kHz_MAX)	on (50 kHz_MAX)	off	off	off
External clock	optional (16MHz_MAX)		optional (16MHz_MAX)	optional (16MHz_MAX)	optional (50 kHz_MAX)	optional (50 kHz_MAX)	optional (50 kHz_MAX)	off	off
Full retention	yes		yes	yes	yes	yes ⁽⁷⁾	yes ⁽⁷⁾	no	no
SVS	always		always	always	opt. ⁽⁸⁾	opt. ⁽⁸⁾	opt. ⁽⁸⁾	opt. ⁽⁸⁾	on ⁽⁹⁾	off ⁽¹⁰⁾
Brownout	always		always	always	always	always	always	always	always

(1) FRAM disabled in FRAM controller

(2) Disabling the FRAM through the FRAM controller decreases the LPM current consumption, but the wake-up time can increase. If the wake-up is for FRAM access (for example, to fetch an interrupt vector), wake-up time is increased. If the wake-up is for an operation other than FRAM access (for example, DMA transfer to RAM), wake-up time is not increased.

(3) All clocks disabled

(4) Controlled by SMCLKOFF

(5) See Section 5.3.1, which describes the use of peripherals in LPM3 and LPM4.

(6) See Table 5-2 for a detailed description of peripherals in high-frequency, low-frequency, or unclocked state.

(7) Using the RAM controller, the RAM can be completely powered down to save leakage; however, all data are lost.

(8) Activated SVS (SVSHE = 1) results in higher current consumption. SVS is not included in typical current consumption.

(9) SVSHE = 1

(10) SVSHE = 0

5.3.1 Peripherals in Low-Power Modes

Peripherals can be in different states that impact the achievable power modes of the device. The states depend on the operational modes of the peripherals. The states are:

A peripheral is in a high-frequency state if it requires or uses a clock with a "high" frequency of more than 50 kHz.
A peripheral is in a low-frequency state if it requires or uses a clock with a "low" frequency of 50 kHz or less.
A peripheral is in an unclocked state if it does not require or use an internal clock.

If the CPU requests a power mode that does not support the current state of all active peripherals, the device does not enter the requested power mode and instead enters a power mode that still supports the current state of the peripherals, unless an external clock is used. If an external clock is used, the application must ensure that the correct frequency range for the requested power mode is selected.

Table 5-2 Peripheral States

PERIPHERAL	IN HIGH-FREQUENCY STATE⁽¹⁾	IN LOW-FREQUENCY STATE⁽²⁾	IN UNCLOCKED STATE⁽³⁾
WDT	Clocked by SMCLK	Clocked by ACLK	Not applicable
DMA⁽⁴⁾	Not applicable	Not applicable	Waiting for a trigger
RTC_C	Not applicable	Clocked by LFXT	Not applicable
LCD_C	Not applicable	Clocked by ACLK or VLOCLK	Not applicable
Timer_A TAx	Clocked by SMCLK or clocked by external clock >50 kHz	Clocked by ACLK or clocked by external clock ≤50 kHz.	Clocked by external clock ≤50 kHz.
Timer_B TBx	Clocked by SMCLK or clocked by external clock >50 kHz	Clocked by ACLK or clocked by external clock ≤50 kHz	Clocked by external clock ≤50 kHz
eUSCI_Ax in UART mode	Clocked by SMCLK	Clocked by ACLK	Waiting for first edge of START bit
eUSCI_Ax in SPI master mode	Clocked by SMCLK	Clocked by ACLK	Not applicable
eUSCI_Ax in SPI slave mode	Clocked by external clock >50 kHz	Clocked by external clock ≤50 kHz	Clocked by external clock ≤50 kHz
eUSCI_Bx in I²C master mode	Clocked by SMCLK or clocked by external clock >50 kHz	Clocked by ACLK or clocked by external clock ≤50 kHz	Not applicable
eUSCI_Bx in I²C slave mode	Clocked by external clock >50 kHz	Clocked by external clock ≤50 kHz	Waiting for START condition or clocked by external clock ≤50 kHz
eUSCI_Bx in SPI master mode	Clocked by SMCLK	Clocked by ACLK	Not applicable
eUSCI_Bx in SPI slave mode	Clocked by external clock >50 kHz	Clocked by external clock ≤50 kHz	Clocked by external clock ≤50 kHz
ESI	Clocked by SMCLK	Clocked by ACLK or ESIOSC	Not applicable
ADC12_B	Clocked by SMCLK or by MODOSC	Clocked by ACLK	Waiting for a trigger
REF_A	Not applicable	Not applicable	Always
COMP_E	Not applicable	Not applicable	Always
CRC⁽⁵⁾	Not applicable	Not applicable	Not applicable
MPY⁽⁵⁾	Not applicable	Not applicable	Not applicable
AES⁽⁵⁾	Not applicable	Not applicable	Not applicable

(1) Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.

(2) Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.

(3) Peripherals are in a state that does not require or does not use an internal clock.

(4) The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power mode will cause a temporary transition into active mode for the time of the transfer.

(5) Operates only during active mode and will delay the transition into a low-power mode until its operation is completed.

5.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4

Most peripherals can be activated to be operational in LPM3 if clocked by ACLK. Some modules are even operational in LPM4 because they do not require a clock to operate (for example, the comparator). Activating a peripheral in LPM3 or LPM4 increases the current consumption due to its active supply current contribution but also due to an additional idle current. To limit the idle current adder certain peripherals are group together. To achieve optimal current consumption try to use modules within one group and to limit the number of groups with active modules. Table 5-3 lists the group for each peripheral. Modules not listed in this table are either already included in the standard LPM3 current consumption specifications or cannot be used in LPM3 or LPM4.

The idle current adder is very small at room temperature (25°C) but increases at high temperatures (95°C). See the I_IDLE parameters in Section 4.7 for details.

Table 5-3 Peripheral Groups

GROUP A	GROUP B	GROUP C	GROUP D
Timer TA0	Timer TA1	Timer TA2	Timer TA3
Comparator	Extended Scan Interface (ESI)	Timer B0	LCD_C
ADC12_B		eUSCI_A0	eUSCI_A1
REF_A		eUSCI_B0
		eUSCI_B1

5.4 Interrupt Vector Table and Signatures

The interrupt vectors, the power-up start address and signatures are in the address range 0FFFFh to 0FF80h. Figure 5-1 summarizes the content of this address range.

MSP430FR5989-EP Interrupts_Signatures_Passwords.gif

Figure 5-1 Interrupt Vectors, Signatures, and Passwords

The power-up start address or reset vector is located at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing to the start address of the application program.

The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 5-4 shows the device-specific interrupt vector locations.

The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as the BSL password (if enabled by the corresponding signature).

The signatures are located at 0FF80h and extend to higher addresses. Signatures are evaluated during device start-up. Table 5-5 shows the device-specific signature locations.

A JTAG password can be programmed starting at address 0FF88h and extending to higher addresses. The password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for the password. The length of the JTAG password depends on the JTAG signature.

See the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide for details.

Table 5-4 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE	INTERRUPT FLAG	SYSTEM INTERRUPT	WORD ADDRESS	PRIORITY
System Reset Power up, Brownout, Supply Supervisor External Reset RST Watchdog time-out (watchdog mode) WDT, FRCTL MPU, CS, PMM password violation FRAM uncorrectable bit error detection MPU segment violation FRAM access time error Software POR, BOR	SVSHIFG PMMRSTIFG WDTIFG WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW UBDIFG MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG ACCTEIFG PMMPORIFG, PMMBORIFG (SYSRSTIV) ⁽¹⁾ ⁽²⁾	Reset	0FFFEh	Highest
System NMI Vacant memory access JTAG mailbox FRAM bit error detection MPU segment violation	VMAIFG JMBINIFG, JMBOUTIFG CBDIFG, UBDIFG MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG (SYSSNIV) ⁽¹⁾ ⁽³⁾	(Non)maskable	0FFFCh
User NMI External NMI Oscillator fault	NMIIFG, OFIFG (SYSUNIV) ⁽¹⁾ ⁽³⁾	(Non)maskable	0FFFAh
Comparator_E	Comparator_E interrupt flags (CEIV) ⁽¹⁾	Maskable	0FFF8h
Timer_B TB0	TB0CCR0.CCIFG	Maskable	0FFF6h
Timer_B TB0	TB0CCR1.CCIFG to TB0CCR6.CCIFG, TB0CTL.TBIFG (TB0IV)⁽¹⁾	Maskable	0FFF4h
Watchdog timer (interval timer mode)	WDTIFG	Maskable	0FFF2h
Extended Scan IF	ESIIFG0 to ESIIFG8 (ESIIV) ⁽¹⁾	Maskable	0FFF0h
eUSCI_A0 receive or transmit	UCA0IFG: UCRXIFG, UCTXIFG (SPI mode) UCA0IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode) (UCA0IV)⁽¹⁾	Maskable	0FFEEh
eUSCI_B0 receive or transmit	UCB0IFG: UCRXIFG, UCTXIFG (SPI mode) UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I²C mode) (UCB0IV)⁽¹⁾	Maskable	0FFECh
ADC12_B	ADC12IFG0 to ADC12IFG31 ADC12LOIFG, ADC12INIFG, ADC12HIIFG, ADC12RDYIFG, ADC12OVIFG, ADC12TOVIFG (ADC12IV) ⁽¹⁾	Maskable	0FFEAh
Timer_A TA0	TA0CCR0.CCIFG	Maskable	0FFE8h
Timer_A TA0	TA0CCR1.CCIFG to TA0CCR2.CCIFG, TA0CTL.TAIFG (TA0IV)⁽¹⁾	Maskable	0FFE6h
eUSCI_A1 receive or transmit	UCA1IFG:UCRXIFG, UCTXIFG (SPI mode) UCA1IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode) (UCA1IV)⁽¹⁾	Maskable	0FFE4h
eUSCI_B1 receive or transmit)	UCB1IFG: UCRXIFG, UCTXIFG (SPI mode) UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I²C mode) (UCB1IV)⁽¹⁾	Maskable	0FFE2h
DMA	DMA0CTL.DMAIFG, DMA1CTL.DMAIFG, DMA2CTL.DMAIFG (DMAIV)⁽¹⁾	Maskable	0FFE0h
Timer_A TA1	TA1CCR0.CCIFG	Maskable	0FFDEh
Timer_A TA1	TA1CCR1.CCIFG to TA1CCR2.CCIFG, TA1CTL.TAIFG (TA1IV)⁽¹⁾	Maskable	0FFDCh
I/O Port P1	P1IFG.0 to P1IFG.7 (P1IV)⁽¹⁾	Maskable	0FFDAh
Timer_A TA2	TA2CCR0.CCIFG	Maskable	0FFD8h
Timer_A TA2	TA2CCR1.CCIFG TA2CTL.TAIFG (TA2IV)⁽¹⁾	Maskable	0FFD6h
I/O Port P2	P2IFG.0 to P2IFG.7 (P2IV) ⁽¹⁾	Maskable	0FFD4h
Timer_A TA3	TA3CCR0.CCIFG	Maskable	0FFD2h
Timer_A TA3	TA3CCR1.CCIFG TA3CTL.TAIFG (TA3IV)⁽¹⁾	Maskable	0FFD0h
I/O Port P3	P3IFG.0 to P3IFG.7 (P3IV) ⁽¹⁾	Maskable	0FFCEh
I/O Port P4	P4IFG.0 to P4IFG.7 (P4IV) ⁽¹⁾	Maskable	0FFCCh
LCD_C (Reserved on MSP430FR5xxx)	LCD_C interrupt flags (LCDCIV) ⁽¹⁾	Maskable	0FFCAh
RTC_C	RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV) ⁽¹⁾	Maskable	0FFC8h
AES	AESRDYIFG	Maskable	0FFC6h	Lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space

(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

Table 5-5 Signatures

SIGNATURE	WORD ADDRESS
IP Encapsulation Signature2	0FF8Ah
IP Encapsulation Signature1 ⁽¹⁾	0FF88h
BSL Signature2	0FF86h
BSL Signature1	0FF84h
JTAG Signature2	0FF82h
JTAG Signature1	0FF80h

(1) Must not contain 0AAAAh if used as JTAG password and IP encapsulation functionality is not desired.

5.5 Bootloader (BSL)

The BSL enables programming of the FRAM or RAM using a UART serial interface (FRxxxx devices) or an I²C interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an user-defined password. Table 5-6 lists the BSL pin requirements. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features of the BSL and its implementation, see MSP430 Programming With the Bootloader (BSL).

Table 5-6 BSL Pin Requirements and Functions

DEVICE SIGNAL	BSL FUNCTION
RST/NMI/SBWTDIO	Entry sequence signal
TEST/SBWTCK	Entry sequence signal
P2.0	Devices with UART BSL (FRxxxx): Data transmit
P2.1	Devices with UART BSL (FRxxxx): Data receive
P1.6	Devices with I²C BSL (FRxxxx1): Data
P1.7	Devices with I²C BSL (FRxxxx1): Clock
VCC	Power supply
VSS	Ground supply

5.6 JTAG Operation

5.6.1 JTAG Standard Interface

The MSP430 family supports the standard JTAG interface, which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO signal is required to interface with MSP430 development tools and device programmers. Table 5-7 lists the JTAG pin requirements. For details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For details on the JTAG implementation in MSP MCUs, see MSP430 Programming With the JTAG Interface.

Table 5-7 JTAG Pin Requirements and Functions

DEVICE SIGNAL	DIRECTION	FUNCTION
PJ.3/TCK	IN	JTAG clock input
PJ.2/TMS	IN	JTAG state control
PJ.1/TDI/TCLK	IN	JTAG data input, TCLK input
PJ.0/TDO	OUT	JTAG data output
TEST/SBWTCK	IN	Enable JTAG pins
RST/NMI/SBWTDIO	IN	External reset
VCC		Power supply
VSS		Ground supply

5.6.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 5-8 lists the Spy-Bi-Wire interface pin requirements. For details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For details on the SBW implementation in MSP MCUs, see MSP430 Programming With the JTAG Interface.

Table 5-8 Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL	DIRECTION	FUNCTION
TEST/SBWTCK	IN	Spy-Bi-Wire clock input
RST/NMI/SBWTDIO	IN, OUT	Spy-Bi-Wire data input/output
VCC		Power supply
VSS		Ground supply

5.7 FRAM

The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in system by the CPU. Features of the FRAM include:

Ultra-low-power ultra-fast-write nonvolatile memory
Byte and word access capability
Programmable wait state generation
Error correction coding (ECC)

NOTE

Wait States

For MCLK frequencies > 8 MHz, wait states must be configured following the flow described in the "FRAM Controller (FRCTRL)" chapter, section "Wait State Control" of the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.

For important software design information regarding FRAM including but not limited to partitioning the memory layout according to application-specific code, constant, and data space requirements, the use of FRAM to optimize application energy consumption, and the use of the memory protection unit (MPU) to maximize application robustness by protecting the program code against unintended write accesses, see MSP430™ FRAM Technology – How To and Best Practices.

5.8 RAM

The RAM is made up of one sector. The sector can be completely powered down in LPM3 and LPM4 to save leakage; however, all data is lost during shutdown.

5.9 Tiny RAM

The Tiny RAM can be used to hold data or a very small stack if the complete RAM is powered down in LPM3 and LPM4.

5.10 Memory Protection Unit Including IP Encapsulation

The FRAM can be protected from inadvertent CPU execution, read or write access by the MPU. Features of the MPU include:

IP Encapsulation with programmable boundaries (prevents reads from "outside" like JTAG or non-IP software) in steps of 1KB.
Main memory partitioning programmable up to three segments in steps of 1KB.
The access rights of each segment (main and information memory) can be individually selected.
Access violation flags with interrupt capability for easy servicing of access violations.

5.11 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be managed using all instructions. For complete module descriptions, see the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.

5.11.1 Digital I/O

Up to eleven 8-bit I/O ports are implemented:

All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all pins of ports P1, P2, P3, and P4.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
Capacitive touch functionality is supported on all pins of ports P1 to P10 and PJ.
No cross-currents during start-up

NOTE

Configuration of Digital I/Os After BOR Reset

To prevent any cross-currents during start-up of the device all port pins are high-impedance with Schmitt triggers and their module functions disabled. To enable the I/O functionality after a BOR reset the ports must be configured first and then the LOCKLPM5 bit must be cleared. For details, see the Configuration After Reset section of the Digital I/O chapter in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.

5.11.2 Oscillator and Clock System (CS)

The clock system includes support for a 32-kHz watch crystal oscillator XT1 (LF), an internal very-low-power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources. The clock system module provides the following clock signals:

Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (LFXT1), the internal low-frequency oscillator (VLO), or a digital external low frequency (<50 kHz) clock source.
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency crystal (HFXT2), the internal digitally controlled oscillator DCO, a 32-kHz watch crystal (LFXT1), the internal low-frequency oscillator (VLO), or a digital external clock source.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources made available to MCLK.

5.11.3 Power-Management Module (PMM)

The primary functions of the PMM are:

Supply regulated voltages to the core logic
Supervise voltages that are connected to the device (at DVCC pins)
Give reset signals to the device during power on and power off

5.11.4 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations.

5.11.5 Real-Time Clock (RTC_C)

The RTC_C module contains an integrated real-time clock (RTC) with the following features implemented:

Calendar mode with leap year correction
General-purpose counter mode

The internal calendar compensates months with less than 31 days and includes leap year correction. The RTC_C also supports flexible alarm functions and offset-calibration hardware. RTC operation is available in LPM3.5 modes to minimize power consumption.

5.11.6 Watchdog Timer (WDT_A)

The primary function of the WDT_A module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. Table 5-9 lists the clocks that can be used by the WDT.

NOTE

In watchdog mode, the watchdog timer prevents entry into LPM3.5 or LPM4.5 because this would deactivate the watchdog.

Table 5-9 WDT_A Clocks

WDTSSEL	NORMAL OPERATION (WATCHDOG AND INTERVAL TIMER MODE)
00	SMCLK
01	ACLK
10	VLOCLK
11	LFMODCLK

5.11.7 System Module (SYS)

The SYS module handles many of the system functions within the device. These system functions include power-on reset and power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootloader entry mechanisms, and configuration management (device descriptors). The SYS module also includes a data exchange mechanism through JTAG called a JTAG mailbox that can be used in the application. Table 5-10 lists the interrupt vector registers of the SYS module.

Table 5-10 System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER	ADDRESS	INTERRUPT EVENT	VALUE	PRIORITY
SYSRSTIV, System Reset	019Eh	No interrupt pending	00h
		Brownout (BOR)	02h	Highest
		RSTIFG RST/NMI (BOR)	04h
		PMMSWBOR software BOR (BOR)	06h
		LPMx.5 wakeup (BOR)	08h
		Security violation (BOR)	0Ah
		Reserved	0Ch
		SVSHIFG SVSH event (BOR)	0Eh
		Reserved	10h
		Reserved	12h
		PMMSWPOR software POR (POR)	14h
		WDTIFG watchdog time-out (PUC)	16h
		WDTPW password violation (PUC)	18h
		FRCTLPW password violation (PUC)	1Ah
		Uncorrectable FRAM bit error detection (PUC)	1Ch
		Peripheral area fetch (PUC)	1Eh
		PMMPW PMM password violation (PUC)	20h
		MPUPW MPU password violation (PUC)	22h
		CSPW CS password violation (PUC)	24h
		MPUSEGPIFG encapsulated IP memory segment violation (PUC)	26h
		MPUSEGIIFG information memory segment violation (PUC)	28h
		MPUSEG1IFG segment 1 memory violation (PUC)	2Ah
		MPUSEG2IFG segment 2 memory violation (PUC)	2Ch
		MPUSEG3IFG segment 3 memory violation (PUC)	2Eh
		ACCTEIFG access time error (PUC)⁽¹⁾	30h
		Reserved	32h to 3Eh	Lowest
SYSSNIV, System NMI	019Ch	No interrupt pending	00h
		Reserved	02h	Highest
		Uncorrectable FRAM bit error detection	04h
		Reserved	06h
		MPUSEGPIFG encapsulated IP memory segment violation	08h
		MPUSEGIIFG information memory segment violation	0Ah
		MPUSEG1IFG segment 1 memory violation	0Ch
		MPUSEG2IFG segment 2 memory violation	0Eh
		MPUSEG3IFG segment 3 memory violation	10h
		VMAIFG Vacant memory access	12h
		JMBINIFG JTAG mailbox input	14h
		JMBOUTIFG JTAG mailbox output	16h
		Correctable FRAM bit error detection	18h
		Reserved	1Ah to 1Eh	Lowest
SYSUNIV, User NMI	019Ah	No interrupt pending	00h
		NMIIFG NMI pin	02h	Highest
		OFIFG oscillator fault	04h
		Reserved	06h
		Reserved	08h
		Reserved	0Ah to 1Eh	Lowest

(1) Indicates incorrect wait state settings.

5.11.8 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC10_B conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 5-11 lists the triggers that can be used to start DMA operation.

Table 5-11 DMA Trigger Assignments⁽¹⁾

TRIGGER	CHANNEL 0	CHANNEL 1	CHANNEL 2
0	DMAREQ	DMAREQ	DMAREQ
1	TA0CCR0 CCIFG	TA0CCR0 CCIFG	TA0CCR0 CCIFG
2	TA0CCR2 CCIFG	TA0CCR2 CCIFG	TA0CCR2 CCIFG
3	TA1CCR0 CCIFG	TA1CCR0 CCIFG	TA1CCR0 CCIFG
4	TA1CCR2 CCIFG	TA1CCR2 CCIFG	TA1CCR2 CCIFG
5	TA2 CCR0 CCIFG	TA2 CCR0 CCIFG	TA2 CCR0 CCIFG
6	TA3 CCR0 CCIFG	TA3 CCR0 CCIFG	TA3 CCR0 CCIFG
7	TB0CCR0 CCIFG	TB0CCR0 CCIFG	TB0CCR0 CCIFG
8	TB0CCR2 CCIFG	TB0CCR2 CCIFG	TB0CCR2 CCIFG
9	Reserved	Reserved	Reserved
10	Reserved	Reserved	Reserved
11	AES Trigger 0	AES Trigger 0	AES Trigger 0
12	AES Trigger 1	AES Trigger 1	AES Trigger 1
13	AES Trigger 2	AES Trigger 2	AES Trigger 2
14	UCA0RXIFG	UCA0RXIFG	UCA0RXIFG
15	UCA0TXIFG	UCA0TXIFG	UCA0TXIFG
16	UCA1RXIFG	UCA1RXIFG	UCA1RXIFG
17	UCA1TXIFG	UCA1TXIFG	UCA1TXIFG
18	UCB0RXIFG (SPI) UCB0RXIFG0 (I²C)	UCB0RXIFG (SPI) UCB0RXIFG0 (I²C)	UCB0RXIFG (SPI) UCB0RXIFG0 (I²C)
19	UCB0TXIFG (SPI) UCB0TXIFG0 (I²C)	UCB0TXIFG (SPI) UCB0TXIFG0 (I²C)	UCB0TXIFG (SPI) UCB0TXIFG0 (I²C)
20	UCB0RXIFG1 (I²C)	UCB0RXIFG1 (I²C)	UCB0RXIFG1 (I²C)
21	UCB0TXIFG1 (I²C)	UCB0TXIFG1 (I²C)	UCB0TXIFG1 (I²C)
22	UCB0RXIFG2 (I²C)	UCB0RXIFG2 (I²C)	UCB0RXIFG2 (I²C)
23	UCB0TXIFG2 (I²C)	UCB0TXIFG2 (I²C)	UCB0TXIFG2 (I²C)
24	UCB1RXIFG (SPI) UCB1RXIFG0 (I²C)	UCB1RXIFG (SPI) UCB1RXIFG0 (I²C)	UCB1RXIFG (SPI) UCB1RXIFG0 (I²C)
25	UCB1TXIFG (SPI) UCB1TXIFG0 (I²C)	UCB1TXIFG (SPI) UCB1TXIFG0 (I²C)	UCB1TXIFG (SPI) UCB1TXIFG0 (I²C)
26	ADC12 end of conversion	ADC12 end of conversion	ADC12 end of conversion
27	Reserved	Reserved	Reserved
28	ESI	ESI	ESI
29	MPY ready	MPY ready	MPY ready
30	DMA2IFG	DMA0IFG	DMA1IFG
31	DMAE0	DMAE0	DMAE0

(1) If a reserved trigger source is selected, no trigger is generated.

5.11.9 Enhanced Universal Serial Communication Interface (eUSCI)

The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I²C, and asynchronous communication protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA.

The eUSCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, and IrDA.

The eUSCI_Bn module provides support for SPI (3 pin or 4 pin) and I²C.

Two eUSCI_A modules and one or two eUSCI_B module are implemented.

5.11.10 Extended Scan Interface (ESI)

The ESI peripheral automatically scans sensors and measures linear or rotational motion with the lowest possible power consumption. The ESI incorporates a V_CC/2 generator, a comparator, and a 12-bit DAC and supports up to four sensors.

5.11.11 Timer_A TA0, Timer_A TA1

TA0 and TA1 are 16-bit timers/counters (Timer_A type) with three capture/compare registers each. TA0 and TA1 can support multiple capture/compares, PWM outputs, and interval timing (see Table 5-12 and Table 5-13). TA0 and TA1 have extensive interrupt capabilities. Interrupts can be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 5-12 Timer_A TA0 Signal Connections

INPUT PORT PIN	DEVICE INPUT SIGNAL	MODULE INPUT SIGNAL	MODULE BLOCK	MODULE OUTPUT SIGNAL	DEVICE OUTPUT SIGNAL	OUTPUT PORT PIN
P1.2 or P6.7 or P7.0	TA0CLK	TACLK	Timer	N/A	N/A
	ACLK (internal)	ACLK
	SMCLK (internal)	SMCLK
P1.2 or P6.7 or P7.0	TA0CLK	INCLK
P1.5	TA0.0	CCI0A	CCR0	TA0	TA0.0	P1.5
P7.1 or P10.1	TA0.0	CCI0B				P7.1
	DV_SS	GND				P10.1
	DV_CC	V_CC
P1.0 or P1.6 or P7.2 or P7.6	TA0.1	CCI1A	CCR1	TA1	TA0.1	P1.0
P1.0 or P1.6 or P7.2 or P7.6	TA0.1	CCI1A				P1.6
	COUT (internal)	CCI1B				P7.2
	COUT (internal)	CCI1B				P7.6
	DV_SS	GND				ADC12 (internal) ADC12SHSx = {1}
	DV_CC	V_CC				ADC12 (internal) ADC12SHSx = {1}
P1.1 or P1.7 or P7.3 or P7.5	TA0.2	CCI2A	CCR2	TA2	TA0.2	P1.1
	ACLK (internal)	CCI2B				P1.7
	DV_SS	GND				P7.3
	DV_CC	V_CC				P7.5

Table 5-13 Timer_A TA1 Signal Connections

INPUT PORT PIN	DEVICE INPUT SIGNAL	MODULE INPUT SIGNAL	MODULE BLOCK	MODULE OUTPUT SIGNAL	DEVICE OUTPUT SIGNAL	OUTPUT PORT PIN
P1.1 or P4.4 or P5.2	TA1CLK	TACLK	Timer	N/A	N/A
	ACLK (internal)	ACLK
	SMCLK (internal)	SMCLK
P1.1 or P4.4 or P5.2	TA1CLK	INCLK
P1.4 or P4.5	TA1.0	CCI0A	CCR0	TA0	TA1.0	P1.4
P5.2 or P10.2	TA1.0	CCI0B				P4.5
	DV_SS	GND				P5.2
	DV_CC	V_CC				P10.2
P1.2 or P3.3 or P4.6 or P5.0	TA1.1	CCI1A	CCR1	TA1	TA1.1	P1.2
P1.2 or P3.3 or P4.6 or P5.0	TA1.1	CCI1A				P4.6
	COUT (internal)	CCI1B				P3.3
	COUT (internal)	CCI1B				P5.0
	DV_SS	GND				ADC12 (internal) ADC12SHSx = {4}
	DV_CC	V_CC				ADC12 (internal) ADC12SHSx = {4}
P1.3 or P4.7 or P5.1 or P7.7	TA1.2	CCI2A	CCR2	TA2	TA1.2	P1.3
	ACLK (internal)	CCI2B				P4.7
	DV_SS	GND				P5.1
	DV_CC	V_CC				P7.7

5.11.12 Timer_A TA2

TA2 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers each and with internal connections only. TA2 can support multiple capture/compares, PWM outputs, and interval timing (see Table 5-14). TA2 has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 5-14 Timer_A TA2 Signal Connections

DEVICE INPUT SIGNAL	MODULE INPUT NAME	MODULE BLOCK	MODULE OUTPUT SIGNAL	DEVICE OUTPUT SIGNAL
COUT (internal)	TACLK	Timer	N/A
ACLK (internal)	ACLK
SMCLK (internal)	SMCLK
From Capacitive Touch I/O 0 (internal)	INCLK
TA3 CCR0 output (internal)	CCI0A	CCR0	TA0	TA3 CCI0A input
ACLK (internal)	CCI0B
DV_SS	GND
DV_CC	V_CC
From Capacitive Touch I/O 0 (internal)	CCI1A	CCR1	TA1	ADC12 (internal) ADC12SHSx = {5}
COUT (internal)	CCI1B
DV_SS	GND
DV_CC	V_CC

5.11.13 Timer_A TA3

TA3 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers each and with internal connections only. TA3 can support multiple capture/compares, PWM outputs, and interval timing (see Table 5-15). TA3 has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 5-15 Timer_A TA3 Signal Connections

DEVICE INPUT SIGNAL	MODULE INPUT NAME	MODULE BLOCK	MODULE OUTPUT SIGNAL	DEVICE OUTPUT SIGNAL
COUT (internal)	TACLK	Timer	N/A
ACLK (internal)	ACLK
SMCLK (internal)	SMCLK
From Capacitive Touch I/O 1 (internal)	INCLK
TA2 CCR0 output (internal)	CCI0A	CCR0	TA0	TA2 CCI0A input
ACLK (internal)	CCI0B
DV_SS	GND
DV_CC	V_CC
From Capacitive Touch I/O 1 (internal)	CCI1A	CCR1	TA1	ADC12 (internal) ADC12SHSx = {6}
COUT (internal)	CCI1B
DV_SS	GND
DV_CC	V_CC
DV_SS	CCI2A	CCR2	TA2
ESIO0 (internal)	CCI2B
DV_SS	GND
DV_CC	V_CC
DV_SS	CCI3A	CCR3	TA3
ESIO1 (internal)	CCI3B
DV_SS	GND
DV_CC	V_CC
DV_SS	CCI4A	CCR4	TA4
ESIO2 (internal)	CCI4B
DV_SS	GND
DV_CC	V_CC

5.11.14 Timer_B TB0

TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers each. TB0 can support multiple capture/compares, PWM outputs, and interval timing (see Table 5-16). TB0 has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 5-16 Timer_B TB0 Signal Connections

INPUT PORT PIN	DEVICE INPUT SIGNAL	MODULE INPUT SIGNAL	MODULE BLOCK	MODULE OUTPUT SIGNAL	DEVICE OUTPUT SIGNAL	OUTPUT PORT PIN
P2.0 or P3.3 or P5.7	TB0CLK	TBCLK	Timer	N/A	N/A
	ACLK (internal)	ACLK
	SMCLK (internal)	SMCLK
P2.0 or P3.3 or P5.7	TB0CLK	INCLK
P3.4	TB0.0	CCI0A	CCR0	TB0	TB0.0	P3.4
P6.4	TB0.0	CCI0B				P6.4
	DV_SS	GND				ADC12 (internal) ADC12SHSx = {2}
	DV_CC	V_CC
P3.5 or P6.5	TB0.1	CCI1A	CCR1	TB1	TB0.1	P3.5
	COUT (internal)	CCI1B				P6.5
	DV_SS	GND				ADC12 (internal) ADC12SHSx = {3}
	DV_CC	V_CC
P3.6 or P6.6	TB0.2	CCI2A	CCR2	TB2	TB0.2	P3.6
	ACLK (internal)	CCI2B				P6.6
	DV_SS	GND
	DV_CC	V_CC
P2.4	TB0.3	CCI3A	CCR3	TB3	TB0.3	P2.4
P3.7	TB0.3	CCI3B				P3.7
	DV_SS	GND
	DV_CC	V_CC
P2.5	TB0.4	CCI4A	CCR4	TB4	TB0.4	P2.5
P2.2	TB0.4	CCI4B				P2.2
	DV_SS	GND
	DV_CC	V_CC
P2.6	TB0.5	CCI5A	CCR5	TB5	TB0.5	P2.6
P2.1	TB0.5	CCI5B				P2.1
	DV_SS	GND
	DV_CC	V_CC
P2.7	TB0.6	CCI6A	CCR6	TB6	TB0.6	P2.7
P2.0	TB0.6	CCI6B				P2.0
	DV_SS	GND
	DV_CC	V_CC

5.11.15 ADC12_B

The ADC12_B module supports fast 12-bit analog-to-digital conversions with differential and single-ended inputs. The module implements a 12-bit SAR core, sample select control, a reference generator, and a conversion result buffer. A window comparator with lower and upper limits allows CPU-independent result monitoring with three window comparator interrupt flags.

Table 5-17 lists the external trigger sources. Table 5-18 lists the available multiplexing between internal and external analog inputs.

Table 5-17 ADC12_B Trigger Signal Connections

ADC12SHSx		CONNECTED TRIGGER SOURCE
BINARY	DECIMAL	CONNECTED TRIGGER SOURCE
000	0	Software (ADC12SC)
001	1	Timer_A TA0 CCR1 output
010	2	Timer_B TB0 CCR0 output
011	3	Timer_B TB0 CCR1 output
100	4	Timer_A TA1 CCR1 output
101	5	Timer_A TA2 CCR1 output
110	6	Timer_A TA3 CCR1 output
111	7	Reserved (DVSS)

Table 5-18 ADC12_B External and Internal Signal Mapping

CONTROL BIT	EXTERNAL (CONTROL BIT = 0)	INTERNAL (CONTROL BIT = 1)
ADC12BATMAP	A31	Battery Monitor
ADC12TCMAP	A30	Temperature Sensor
ADC12CH0MAP	A29	N/A⁽¹⁾
ADC12CH1MAP	A28	N/A⁽¹⁾
ADC12CH2MAP	A27	N/A⁽¹⁾
ADC12CH3MAP	A26	N/A⁽¹⁾

(1) N/A = No internal signal available on this device.

5.11.16 Comparator_E

The primary function of the Comparator_E module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals.

5.11.17 CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 signature is based on the CRC-CCITT standard.

5.11.18 CRC32

The CRC32 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC32 signature is based on the ISO 3309 standard.

5.11.19 AES256 Accelerator

The AES accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256-bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.

5.11.20 True Random Seed

The Device Descriptor Information (TLV) section contains a 128-bit true random seed that can be used to implement a deterministic random number generator.

5.11.21 Shared Reference (REF_A)

The reference module (REF_A) generates all critical reference voltages that can be used by the various analog peripherals in the device.

5.11.22 LCD_C

The LCD_C driver generates the segment and common signals required to drive a liquid crystal display (LCD). The LCD_C controller has dedicated data memories to hold segment drive information. Common and segment signals are generated as defined by the mode. Static and 2-mux to 8-mux LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The module also provides an automatic blinking capability for individual segments in static, 2-mux, 3-mux, and 4-mux modes.

To reduce system noise, the charge pump can be temporarily disabled. Table 5-19 lists the available automatic charge pump disable options.

Table 5-19 LCD Automatic Charge Pump Disable Bits (LCDCPDISx)

CONTROL BIT	DESCRIPTION
LCDCPDIS0	LCD charge pump disable during ADC12 conversion 0b = LCD charge pump not automatically disabled during conversion 1b = LCD charge pump automatically disabled during conversion
LCDCPDIS1 to LCDCPDIS7	No functionality

5.11.23 Embedded Emulation

5.11.23.1 Embedded Emulation Module (EEM)

The EEM supports real-time in-system debugging. The S version of the EEM has the following features:

Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers that can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level

5.11.23.2 EnergyTrace++™ Technology

These MCUs implement circuitry to support EnergyTrace++ technology. The EnergyTrace++ technology allows you to observe information about the internal states of the microcontroller. These states include the CPU Program Counter (PC), the ON or OFF status of the peripherals and the system clocks (regardless of the clock source), and the low-power mode currently in use. These states can always be read by a debug tool, even when the microcontroller sleeps in LPMx.5 modes.

The activity of the following modules can be observed:

MPY is calculating.
WDT is counting.
RTC is counting.
ADC: a sequence, sample, or conversion is active.
REF: REFBG or REFGEN active and BG in static mode.
COMP is on.
AES is encrypting or decrypting.
eUSCI_A0 is transferring (receiving or transmitting) data.
eUSCI_A1 is transferring (receiving or transmitting) data.
eUSCI_B0 is transferring (receiving or transmitting) data.
eUSCI_B1 is transferring (receiving or transmitting) data.
TB0 is counting.
TA0 is counting.
TA1 is counting.
TA2 is counting.
TA3 is counting.
LCD: timing generator is active.
ESI:
- ESI is active using LF clock source
- ESI is active using HF clock source

5.11.24 Input/Output Diagrams

5.11.24.1 Digital I/O Functionality – Ports P1 to P10

The port pins provide the following features:

Interrupt and wakeup from LPMx.5 capability for ports P1, P2, P3, and P4
Capacitive touch functionality (see Section 5.11.24.2)
Up to three digital module input or output functions
LCD segment functionality (not all pins, package dependent)

Figure 5-2 shows the features and the corresponding control logic (not including the capacitive touch logic). It is applicable for all port pins P1.0 to P10.2 unless a dedicated diagram is available in the following sections. The module functions provided per pin and whether the direction is controlled by the module or by the port direction register for the selected secondary function are described in the pin function tables.

A. The inputs from several pins toward a module are ORed together.

B. The direction is controlled either by the connected module or by the corresponding PxDIR.y bit. See the pin function tables.

NOTE:

Functional representation only.

Figure 5-2 General Port Pin Diagram

5.11.24.2 Capacitive Touch Functionality Ports P1 to P10 and PJ

Figure 5-3 shows the Capacitive Touch functionality that all port pins provide. The Capacitive Touch functionality is controlled using the Capacitive Touch I/O control registers CAPTIO0CTL and CAPTIO1CTL as described in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide. The Capacitive Touch functionality is not shown in the other pin diagrams.

NOTE:

Functional representation only.

Figure 5-3 Capacitive Touch I/O Diagram

5.11.24.3 Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger

Figure 5-4 shows the port diagram. summarizes the selection of the pin function.

A. The inputs from several pins toward a module are ORed together.

NOTE:

Functional representation only.

Figure 5-4 Port P1 (P1.0 to P1.3) Diagram

Port P1 (P1.0 to P1.3) Pin Functions

PIN NAME (P1.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P1.x)	x	FUNCTION	P1DIR.x	P1SEL1.x	P1SEL0.x
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/ VREF-/VeREF-	0	P1.0 (I/O)	I: 0; O: 1	0	0
		TA0.CCI1A	0	0	1
		TA0.1	1	0	1
		DMAE0	0	1	0
		RTCCLK⁽⁶⁾	1	1	0
		A0, C0, VREF-, VeREF- ⁽⁴⁾ ⁽⁵⁾	X	1	1
P1.1/TA0.2/TA1CLK/COUT/A1/C1/ VREF+/VeREF+	1	P1.1 (I/O)	I: 0; O: 1	0	0
		TA0.CCI2A	0	0	1
		TA0.2	1	0	1
		TA1CLK	0	1	0
		COUT⁽⁷⁾	1	1	0
		A1, C1, VREF+, VeREF+ ⁽⁴⁾ ⁽⁵⁾	X	1	1
P1.2/TA1.1/TA0CLK/COUT/A2/C2	2	P1.2 (I/O)	I: 0; O: 1	0	0
		TA1.CCI1A	0	0	1
		TA1.1	1	0	1
		TA0CLK	0	1	0
		COUT⁽⁸⁾	1	1	0
		A2, C2 ⁽⁴⁾ ⁽⁵⁾	X	1	1
P1.3/TA1.2/ESITEST4/A3/C3	3	P1.3 (I/O)	I: 0; O: 1	0	0
		TA1.CCI2A	0	0	1
		TA1.2	1	0	1
		N/A	0	1	0
		ESITEST4	1	1	0
		A3, C3 ⁽⁴⁾ ⁽⁵⁾	X	1	1

(1) X = Don't care.

(2) Direction controlled by eUSCI_B0 module.

(3) Direction controlled by eUSCI_A0 module.

(4) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

(5) Setting the CEPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Selecting the Cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated CEPD.x bit.

(6) Do not use this pin as RTCCLK output if the DMAE0 functionality is used on any other pin. Select an alternative RTCCLK output pin.

(7) Do not use this pin as COUT output if the TA1CLK functionality is used on any other pin. Select an alternative COUT output pin.

(8) Do not use this pin as COUT output if the TA0CLK functionality is used on any other pin. Select an alternative COUT output pin.

5.11.24.4 Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger

For the pin diagram, see Figure 5-2. summarizes the selection of the pin function.

Port P1 (P1.4 to P1.7) Pin Functions

PIN NAME (P1.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P1.x)	x	FUNCTION	P1DIR.x	P1SEL1.x	P1SEL0.x	LCDSz
P1.4/UCB0CLK/UCA0STE/TA1.0/Sz	4	P1.4 (I/O)	I: 0; O: 1	0	0	0
		UCB0CLK	X ⁽²⁾	0	1	0
		UCA0STE	X ⁽³⁾	1	0	0
		TA1.CCI0A	0	1	1	0
		TA1.0	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P1.5/UCB0STE/UCA0CLK/TA0.0/Sz	5	P1.5 (I/O)	I: 0; O: 1	0	0	0
		UCB0STE	X ⁽²⁾	0	1	0
		UCA0CLK	X ⁽³⁾	1	0	0
		TA0.CCI0A	0	1	1	0
		TA0.0	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P1.6/UCB0SIMO/UCB0SDA/TA0.1/ Sz	6	P1.6 (I/O)	I: 0; O: 1	0	0	0
		UCB0SIMO/UCB0SDA	X ⁽²⁾	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		TA0.CCI1A	0	1	1	0
		TA0.1	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P1.7/UCB0SOMI/UCB0SCL/TA0.2/ Sz	7	P1.7 (I/O)	I: 0; O: 1	0	0	0
		UCB0SOMI/UCB0SCL	X ⁽²⁾	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		TA0.CCI2A	0	1	1	0
		TA0.2	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

(1) The associated LCD segment is package dependent. See the Signal Descriptions tables and Pin Diagrams figures.

5.11.24.5 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger

For the pin diagram, see Figure 5-2. summarizes the selection of the pin function.

Port P2 (P2.0 to P2.3) Pin Functions

PIN NAME (P2.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P2.x)	x	FUNCTION	P2DIR.x	P2SEL1.x	P2SEL0.x	LCDSz
P2.0/UCA0SIMO/UCA0TXD/TB0.6/ TB0CLK/Sz	0	P2.0 (I/O)	I: 0; O: 1	0	0	0
		UCA0SIMO/UCA0TXD	X ⁽¹⁾	0	1	0
		TB0.CCI6B	0	1	0	0
		TB0.6	1	1	0	0
		TB0CLK	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P2.1/UCA0SOMI/UCA0RXD/TB0.5/ DMAE0/Sz	1	P2.1 (I/O)	I: 0; O: 1	0	0	0
		UCA0SOMI/UCA0RXD	X ⁽¹⁾	0	1	0
		TB0.CCI5B	0	1	0	0
		TB0.5	1	1	0	0
		DMA0E	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P2.2/UCA0CLK/TB0.4/RTCCLK/Sz	2	P2.2 (I/O)	I: 0; O: 1	0	0	0
		UCA0CLK	X ⁽¹⁾	0	1	0
		TB0.CCI4B	0	1	0	0
		TB0.4	1	1	0	0
		N/A	0	1	1	0
		RTCCLK	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P2.3/UCA0STE/TB0OUTH/Sz	3	P2.3 (I/O)	I: 0; O: 1	0	0	0
		UCA0STE	X ⁽¹⁾	0	1	0
		TB0OUTH	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

(1) Direction controlled by eUSCI_A0 module.

5.11.24.6 Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger

Figure 5-5 shows the port diagram. summarizes the selection of the pin function.

A. The inputs from several pins toward a module are ORed together.

NOTE:

Functional representation only.

Figure 5-5 Port P2 (P2.4 to P2.7) Diagram

Port P2 (P2.4 to P2.7) Pin Functions

PIN NAME (P2.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P2.x)	x	FUNCTION	P2DIR.x	P2SEL1.x	P2SEL0.x	LCDSz
P2.4/TB0.3/COM4/Sz	4	P2.4 (I/O)	I: 0; O: 1	0	0	0
		TB0.CCI3A	0	0	1	0
		TB0.3	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		COM4	X	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P2.5/TB0.4/COM5/Sz	5	P2.5 (I/O)	I: 0; O: 1	0	0	0
		TB0.CCI4A	0	0	1	0
		TB0.4	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		COM5	X	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P2.6/TB0.5/ESIC1OUT/COM6/Sx	6	P2.6 (I/O)	I: 0; O: 1	0	0	0
		TB0.CCI5A	0	0	1	0
		TB0.5	1	0	1	0
		N/A	0	1	0	0
		ESIC1OUT	1	1	0	0
		COM6	X	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P2.7/TB0.6/ESIC2OUT/COM7/Sx	7	P2.7 (I/O)	I: 0; O: 1	0	0	0
		TB0.CCI6A	0	0	1	0
		TB0.6	1	0	1	0
		N/A	0	1	0	0
		ESIC2OUT	1	1	0	0
		COM7	X	1	1	0
		Sz ⁽¹⁾	X	X	X	1

5.11.24.7 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger

For the pin diagram, see Figure 5-2. and summarize the selection of the pin function.

Port P3 (P3.0 to P3.3) Pin Functions

PIN NAME (P3.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P3.x)	x	FUNCTION	P3DIR.x	P3SEL1.x	P3SEL0.x	LCDSz
P3.0/UCB1CLK/Sz	0	P3.0 (I/O)	I: 0; O: 1	0	0	0
		UCB1CLK	X ⁽¹⁾	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P3.1/UCB1SIMO/UCB1SDA/Sz	1	P3.1 (I/O)	I: 0; O: 1	0	0	0
		UCB1SIMO/UCB1SDA	X ⁽¹⁾	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P3.2/UCB1SOMI/UCB1SCL/Sz	2	P3.2 (I/O)	I: 0; O: 1	0	0	0
		UCB1SOMI/UCB1SCL	X ⁽¹⁾	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
			0	1	1	0
			1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P3.3/TA1.1/TB0CLK/Sz	3	P3.3 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		TA1.CCI1A	0	1	0	0
		TA1.1	1	1	0	0
		TB0CLK	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

(1) Direction controlled by eUSCI_B1 module.

(2) Direction controlled by eUSCI_A1 module.

Port P3 (P3.4 to P3.7) Pin Functions

PIN NAME (P3.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P3.x)	x	FUNCTION	P3DIR.x	P3SEL1.x	P3SEL0.x	LCDSz
P3.4/UCA1SIMO/UCA1TXD/TB0.0/ Sz	4	P3.4 (I/O)	I: 0; O: 1	0	0	0
		UCA1SIMO/UCA1TXD	X ⁽²⁾	0	1	0
		TB0CCI0A	0	1	0	0
		TB0.0	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P3.5/UCA1SOMI/UCA1RXD/TB0.1/ Sz	5	P3.5 (I/O)	I: 0; O: 1	0	0	0
		UCA1SOMI/UCA1RXD	X ⁽²⁾	0	1	0
		TB0CCI1A	0	1	0	0
		TB0.1	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P3.6/UCA1CLK/TB0.2/Sz	6	P3.6 (I/O)	I: 0; O: 1	0	0	0
		UCA1CLK	X ⁽²⁾	0	1	0
		TB0CCI2A	0	1	0	0
		TB0.2	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P3.7/UCA1STE/TB0.3/Sz	7	P3.7 (I/O)	I: 0; O: 1	0	0	0
		UCA1STE	X ⁽²⁾	0	1	0
		TB0CCI3B	0	1	0	0
		TB0.3	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

5.11.24.8 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger

For the pin diagram, see Figure 5-2. and summarize the selection of the pin function.

Port P4 (P4.0 to P4.3) Pin Functions

PIN NAME (P4.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P4.x)	x	FUNCTION	P4DIR.x	P4SEL1.x	P4SEL0.x	LCDSz
P4.0/UCB1SIMO/UCB1SDA/MCLK/ Sz	0	P4.0 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		UCB1SIMO/UCB1SDA	X ⁽¹⁾	1	0	0
		N/A	0	1	1	0
		MCLK	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P4.1/UCB1SOMI/UCB1SCL/ACLK/ Sz	1	P4.1 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		UCB1SOMI/UCB1SCL	X ⁽¹⁾	1	0	0
		N/A	0	1	1	0
		ACLK	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P4.2/UCA0SIMO/UCA0TXD/ UCB1CLK/Sz	2	P4.2 (I/O)	I: 0; O: 1	0	0	0
		UCA0SIMO/UCA0TXD	X ⁽¹⁾	0	1	0
		UCB1CLK	X ⁽¹⁾	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P4.3/UCA0SOMI/UCA0RXD/ UCB1STE/Sz	3	P4.3 (I/O)	I: 0; O: 1	0	0	0
		UCA0SOMI/UCA0RXD	X ⁽¹⁾	0	1	0
		UCB1STE	X ⁽¹⁾	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

Port P4 (P4.4 to P4.7) Pin Functions

PIN NAME (P4.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P4.x)	x	FUNCTION	P4DIR.x	P4SEL1.x	P4SEL0.x	LCDSz
P4.4/UCB1STE/TA1CLK/Sz	4	P4.4 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		UCB1STE	X ⁽¹⁾	1	0	0
		TA1CLK	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P4.5/UCB1CLK/TA1.0/Sz	5	P4.5 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		UCB1CLK	X ⁽¹⁾	1	0	0
		TA1CCI0A	0	1	1	0
		TA1.0	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P4.6/UCB1SIMO/UCB1SDA/TA1.1/ Sz	6	P4.6 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		UCB1SIMO/UCB1SDA	X ⁽¹⁾	1	0	0
		TA1CCI1A	0	1	1	0
		TA1.1	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P4.7/UCB1SOMI/UCB1SCL/TA1.2/ Sz	7	P4.7 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		UCB1SOMI/UCB1SCL	X ⁽¹⁾	1	0	0
		TA1CCI2A	0	1	1	0
		TA1.2	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

5.11.24.9 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger

For the pin diagram, see Figure 5-2. and summarize the selection of the pin function.

Port P5 (P5.0 to P5.3) Pin Functions

PIN NAME (P5.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P5.x)	x	FUNCTION	P5DIR.x	P5SEL1.x	P5SEL0.x	LCDSz
P5.0/TA1.1/MCLK/Sz	0	P5.0 (I/O)	I: 0; O: 1	0	0	0
		TA1CCI1A	0	0	1	0
		TA1.1	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		MCLK	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P5.1/TA1.2/Sz	1	P5.1 (I/O)	I: 0; O: 1	0	0	0
		TA1CCI2A	0	0	1	0
		TA1.2	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		N/A	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P5.2/TA1.0/TA1CLK/ACLK/Sz	2	P5.2 (I/O)	I: 0; O: 1	0	0	0
		TA1CCI0B	0	0	1	0
		TA1.0	1	0	1	0
		TA1CLK	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		ACLK	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P5.3/UCB1STE/Sz	3	P5.3 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		UCB1STE	X ⁽¹⁾	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

Port P5 (P5.4 to P5.7) Pin Functions

PIN NAME (P5.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P5.x)	x	FUNCTION	P5DIR.x	P5SEL1.x	P5SEL0.x	LCDSz
P5.4/UCA1SIMO/UCA1TXD/Sz	4	P5.4 (I/O)	I: 0; O: 1	0	0	0
		UCA1SIMO/UCA1TXD	X ⁽²⁾	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P5.5/UCA1SOMI/UCA1RXD/Sz	5	P5.5 (I/O)	I: 0; O: 1	0	0	0
		UCA1SOMI/UCA1RXD	X ⁽²⁾	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P5.6/UCA1CLK/Sz	6	P5.6 (I/O)	I: 0; O: 1	0	0	0
		UCA1CLK	X ⁽²⁾	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P5.7/UCA1STE/TB0CLK/Sz	7	P5.7 (I/O)	I: 0; O: 1	0	0	0
		UCA1STE	X ⁽²⁾	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		TB0CLK	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

5.11.24.10 Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger

Figure 5-6 shows the port diagram. and summarize the selection of the pin function.

A. The inputs from several pins toward a module are ORed together.

NOTE:

Functional representation only.

Figure 5-6 Port P6 (P6.0 to P6.6) Diagram

Port P6 (P6.0 to P6.2) Pin Functions

PIN NAME (P6.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P6.x)	x	FUNCTION	P6DIR.x	P6SEL1.x	P6SEL0.x	LCDSz
P6.0/R23	0	P6.0 (I/O)	I: 0; O: 1	0	0	–
		N/A	0	0	1	–
		Internally tied to DVSS	1	0	1	–
		N/A	0	1	0	–
		Internally tied to DVSS	1	1	0	–
		R23 ⁽¹⁾	X	1	1	–
P6.1/R13/LCDREF	1	P6.1 (I/O)	I: 0; O: 1	0	0	–
		N/A	0	0	1	–
		Internally tied to DVSS	1	0	1	–
		N/A	0	1	0	–
		Internally tied to DVSS	1	1	0	–
		R13/LCDREF ⁽¹⁾	X	1	1	–
P6.2/COUT/R03	2	P6.2 (I/O)	I: 0; O: 1	0	0	–
		N/A	0	0	1	–
		COUT	1	0	1	–
		N/A	0	1	0	–
		Internally tied to DVSS	1	1	0	–
		R03 ⁽¹⁾	X	1	1	–

(1) Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

Port P6 (P6.3 to P6.6) Pin Functions

PIN NAME (P6.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P6.x)	x	FUNCTION	P6DIR.x	P6SEL1.x	P6SEL0.x	LCDSz
P6.3/COM0	3	P6.3 (I/O)	I: 0; O: 1	0	0	–
		N/A	0	0	1	–
		Internally tied to DVSS	1	0	1	–
		N/A	0	1	0	–
		Internally tied to DVSS	1	1	0	–
		COM0 ⁽¹⁾	X	1	1	–
P6.4/TB0.0/COM1	4	P6.4 (I/O)	I: 0; O: 1	0	0	–
		TB0CCI0B	0	0	1	–
		TB0.0	1	0	1	–
		N/A	0	1	0	–
		Internally tied to DVSS	1	1	0	–
		COM1 ⁽¹⁾	X	1	1	–
P6.5/TB0.1/COM2	5	P6.5 (I/O)	I: 0; O: 1	0	0	–
		TB0CCI1A	0	0	1	–
		TB0.1	1	0	1	–
		N/A	0	1	0	–
		Internally tied to DVSS	1	1	0	–
		COM2 ⁽¹⁾	X	1	1	–
P6.6/TB0.2/COM3	6	P6.6 (I/O)	I: 0; O: 1	0	0	–
		TB0CCI2A	0	0	1	–
		TB0.2	1	0	1	–
		N/A	0	1	0	–
		Internally tied to DVSS	1	1	0	–
		COM3 ⁽¹⁾	X	1	1	–

5.11.24.11 Port P6 (P6.7) Input/Output With Schmitt Trigger

For the pin diagram, see Figure 5-2. summarizes the selection of the pin function.

Port P6 (P6.7) Pin Functions

PIN NAME (P6.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P6.x)	x	FUNCTION	P6DIR.x	P6SEL1.x	P6SEL0.x	LCDSz
P6.7/TA0CLK/Sz	7	P6.7 (I/O)	I: 0; O: 1	0	0	0
		TA0CLK	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

5.11.24.12 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger

For the pin diagram, see Figure 5-2. and summarize the selection of the pin function.

Port P7 (P7.0 to P7.3) Pin Functions

PIN NAME (P7.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P7.x)	x	FUNCTION	P7DIR.x	P7SEL1.x	P7SEL0.x	LCDSz
P7.0/TA0CLK/Sz	0	P7.0 (I/O)	I: 0; O: 1	0	0	0
		TA0CLK	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P7.1/TA0.0/ACLK/Sz	1	P7.1 (I/O)	I: 0; O: 1	0	0	0
		TA0CCI0B	0	0	1	0
		TA0.0	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		ACLK	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P7.2/TA0.1/Sz	2	P7.2 (I/O)	I: 0; O: 1	0	0	0
		TA0CCI1A	0	0	1	0
		TA0.1	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		N/A	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P7.3/TA0.2/Sz	3	P7.3 (I/O)	I: 0; O: 1	0	0	0
		TA0CCI2A	0	0	1	0
		TA0.2	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

Port P7 (P7.4 to P7.7) Pin Functions

PIN NAME (P7.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P7.x)	x	FUNCTION	P7DIR.x	P7SEL1.x	P7SEL0.x	LCDSz
P7.4/SMCLK/Sz	4	P7.4 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		SMCLK	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P7.5/TA0.2/Sz	5	P7.5 (I/O)	I: 0; O: 1	0	0	0
		TA0CCI2A	0	0	1	0
		TA0.2	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P7.6/TA0.1/Sz	6	P7.6 (I/O)	I: 0; O: 1	0	0	0
		TA0CCI1A	0	0	1	0
		TA0.1	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P7.7/TA1.2/TB0OUTH/Sz	7	P7.7 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		TA1.CCI2A	0	1	0	0
		TA1.2	1	1	0	0
		TB0OUTH	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

5.11.24.13 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger

For the pin diagram, see Figure 5-2. summarizes the selection of the pin function.

Port P8 (P8.0 to P8.3) Pin Functions

PIN NAME (P8.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P8.x)	x	FUNCTION	P8DIR.x	P8SEL1.x	P8SEL0.x	LCDSz
P8.0/RTCCLK/Sz	0	P8.0 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		RTCCLK	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P8.1/DMAE0/Sz	1	P8.1 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		DMA0E	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P8.2/Sz	2	P8.2 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P8.3/MCLK/Sz	3	P8.3 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		MCLK	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

5.11.24.14 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger

Figure 5-7 shows the port diagram. summarizes the selection of the pin function.

NOTE:

Functional representation only.

Figure 5-7 Port P8 (P8.4 to P8.7) Diagram

Port P8 (P8.4 to P8.7) Pin Functions

PIN NAME (P8.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P8.x)	x	FUNCTION	P8DIR.x	P8SEL1.x	P8SEL0.x
P8.4/A7/C7	4	P8.4 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		N/A	0	1	0
		Internally tied to DVSS	1	1	0
		A7/C7 ⁽¹⁾ ⁽⁵⁾	X	1	1
P8.5/A6/C6	5	P8.5 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		N/A	0	1	0
		Internally tied to DVSS	1	1	0
		A6/C6 ⁽¹⁾ ⁽⁵⁾	X	1	1
P8.6/A5/C5	6	P8.6 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		N/A	0	1	0
		Internally tied to DVSS	1	1	0
		A5/C5 ⁽¹⁾ ⁽⁵⁾	X	1	1
P8.7/A4/C4	7	P8.7 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		N/A	0	1	0
		Internally tied to DVSS	1	1	0
		A4/C4 ⁽¹⁾ ⁽⁵⁾	X	1	1

(1) Setting P8SEL1.x and P8SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

5.11.24.15 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger

Figure 5-8 shows the port diagram. summarizes the selection of the pin function.

NOTE:

Functional representation only.

Figure 5-8 Port P9 (P9.0 to P9.3) Diagram

Port P9 (P9.0 to P9.3) Pin Functions

PIN NAME (P9.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P9.x)	x	FUNCTION	P9DIR.x	P9SEL1.x	P9SEL0.x
P9.0/ESICH0/ESITEST0/A8/C8	0	P9.0 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		ESITEST0⁽¹⁾	X	1	0
		ESICH0/A8/C8 ⁽¹⁾⁽⁵⁾⁽²⁾	X	1	1
P9.1/ESICH1/ESITEST1/A9/C9	1	P9.1 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		ESITEST1⁽¹⁾	X	1	0
		ESICH1/A9/C9 ⁽¹⁾⁽⁵⁾⁽²⁾	X	1	1
P9.2/ESICH2/ESITEST2/A10/C10	2	P9.2 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		ESITEST2⁽¹⁾	X	1	0
		ESICH2/A10/C10 ⁽¹⁾⁽⁵⁾⁽²⁾	X	1	1
P9.3/ESICH3/ESITEST3/A11/C11	3	P9.3 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		ESITEST3⁽¹⁾	X	1	0
		ESICH3/A11/C11 ⁽¹⁾ ⁽⁵⁾⁽²⁾	X	1	1

(1) Setting P9SEL1.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

(2) Depending on the configuration of the ESI module other ESICHx pins are stimulated as well and thus should have the input Schmitt triggers disabled (with P9SEL1.x = 1) and cannot be used as digital I/O, ADC or comparator inputs.

5.11.24.16 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger

Figure 5-9 shows the port diagram. summarizes the selection of the pin function.

NOTE:

Functional representation only.

Figure 5-9 Port P9 (P9.4 to P9.7) Diagram

Port P9 (P9.4 to P9.7) Pin Functions

PIN NAME (P9.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P9.x)	x	FUNCTION	P9DIR.x	P9SEL1.x	P9SEL0.x
P9.4/ESICI0/A12/C12	4	P9.4 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		N/A	0	1	0
		Internally tied to DVSS	1	1	0
		ESICI0/A12/C12 ⁽¹⁾ ⁽⁵⁾⁽²⁾	X	1	1
P9.5/ESICI1/A13/C13	5	P9.5 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		N/A	0	1	0
		Internally tied to DVSS	1	1	0
		ESICI1/A13/C13 ⁽¹⁾ ⁽⁵⁾⁽²⁾	X	1	1
P9.6/ESICI2/A14/C14	6	P9.6 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		N/A	0	1	0
		Internally tied to DVSS	1	1	0
		ESICI2/A14/C14 ⁽¹⁾ ⁽⁵⁾⁽²⁾	X	1	1
P9.7/ESICI3/A15/C15	7	P9.7 (I/O)	I: 0; O: 1	0	0
		N/A	0	0	1
		Internally tied to DVSS	1	0	1
		N/A	0	1	0
		Internally tied to DVSS	1	1	0
		ESICI3/A15/C15 ⁽¹⁾ ⁽⁵⁾⁽²⁾	X	1	1

(1) Setting P9SEL1.x and P9SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.

(2) Depending on the configuration of the ESI module, other ESICI2/ pins are used, and thus should have the input Schmitt triggers disabled (with P9SEL1.x = 1 and P9SEL0.x = 1) and cannot be used as digital I/O, ADC, or comparator inputs.

5.11.24.17 Port P10 (P10.0 to P10.2) Input/Output With Schmitt Trigger

For the pin diagram, see Figure 5-2. summarizes the selection of the pin function.

Port P10 (P10.0 to P10.2) Pin Functions

PIN NAME (P10.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (P10.x)	x	FUNCTION	P10DIR.x	P10SEL1.x	P10SEL0.x	LCDSz
P10.0/SMCLK/Sz	0	P10.0 (I/O)	I: 0; O: 1	0	0	0
		N/A	0	0	1	0
		Internally tied to DVSS	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		SMCLK	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P10.1/TA0.0/Sz	1	P10.1 (I/O)	I: 0; O: 1	0	0	0
		TA0.CCI0B	0	0	1	0
		TA0.0	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		Internally tied to DVSS	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1
P10.2/TA1.0/SMCLK/Sz	2	P10.2 (I/O)	I: 0; O: 1	0	0	0
		TA1.CCI0B	0	0	1	0
		TA1.0	1	0	1	0
		N/A	0	1	0	0
		Internally tied to DVSS	1	1	0	0
		N/A	0	1	1	0
		SMCLK	1	1	1	0
		Sz ⁽¹⁾	X	X	X	1

5.11.24.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger

Figure 5-10 and Figure 5-11 show the port diagrams. summarizes the selection of the pin function.

NOTE:

Functional representation only.

Figure 5-10 Port PJ (PJ.4) Diagram

NOTE:

Functional representation only.

Figure 5-11 Port PJ (PJ.5) Diagram

Port PJ (PJ.4 and PJ.5) Pin Functions

PIN NAME (PJ.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (PJ.x)	x	FUNCTION	PJDIR.x	PJSEL1.5	PJSEL0.5	PJSEL1.4	PJSEL0.4	LFXT BYPASS
PJ.4/LFXIN	4	PJ.4 (I/O)	I: 0; O: 1	X	X	0	0	X
		N/A	0	X	X	1	X	X
		Internally tied to DVSS	1	X	X	1	X	X
		LFXIN crystal mode ⁽²⁾	X	X	X	0	1	0
		LFXIN bypass mode ⁽²⁾	X	X	X	0	1	1
PJ.5/LFXOUT	5	PJ.5 (I/O)	I: 0; O: 1	0	0	0	0	0
						1	X	0
						X	X	1⁽³⁾
		N/A	0	see⁽¹⁾	see⁽¹⁾	0	0	0
						1	X	0
						X	X	1⁽³⁾
		Internally tied to DVSS	1	see⁽¹⁾	see⁽¹⁾	0	0	0
						1	X	0
						X	X	1⁽³⁾
		LFXOUT crystal mode ⁽²⁾	X	X	X	0	1	0

(1) With PJSEL0.5 = 1 or PJSEL1.5 =1 the general-purpose I/O functionality is disabled. No input function is available. When configured as output, the pin is actively pulled to zero.

(2) Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When LFXTBYPASS = 0, PJ.4 and PJ.5 are configured for crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When LFXTBYPASS = 1, PJ.4 is configured for bypass operation and PJ.5 is configured as general-purpose I/O.

(3) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.

5.11.24.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger

Figure 5-12 and Figure 5-13 show the port diagrams. summarizes the selection of the pin function.

NOTE:

Functional representation only.

Figure 5-12 Port PJ (PJ.6) Diagram

NOTE:

Functional representation only.

Figure 5-13 Port PJ (PJ.7) Diagram

Port PJ (PJ.6 and PJ.7) Pin Functions

PIN NAME (PJ.x)	x	FUNCTION	CONTROL BITS AND SIGNALS⁽¹⁾
PIN NAME (PJ.x)	x	FUNCTION	PJDIR.x	PJSEL1.7	PJSEL0.7	PJSEL1.6	PJSEL0.6	HFXT BYPASS
PJ.6/HFXIN	6	PJ.6 (I/O)	I: 0; O: 1	X	X	0	0	X
		N/A	0	X	X	1	X	X
		Internally tied to DVSS	1	X	X	1	X	X
		HFXIN crystal mode ⁽²⁾	X	X	X	0	1	0
		HFXIN bypass mode ⁽²⁾	X	X	X	0	1	1
PJ.7/HFXOUT	7	PJ.7 (I/O)	I: 0; O: 1	0	0	0	0	0
						1	X	0
						X	X	1⁽³⁾
		N/A	0	see⁽¹⁾	see⁽¹⁾	0	0	0
						1	X	0
						X	X	1⁽³⁾
		Internally tied to DVSS	1	see⁽¹⁾	see⁽¹⁾	0	0	0
						1	X	0
						X	X	1⁽³⁾
		HFXOUT crystal mode ⁽²⁾	X	X	X	0	1	0

(1) With PJSEL0.7 = 1 or PJSEL1.7 =1 the general-purpose I/O functionality is disabled. No input function is available. When configured as output, the pin is actively pulled to zero.

(2) Setting PJSEL1.6 = 0 and PJSEL0.6 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.6 and PJ.7 are configured for crystal operation and PJSEL1.6 and PJSEL0.7 are don't care. When HFXTBYPASS = 1, PJ.6 is configured for bypass operation and PJ.7 is configured as general-purpose I/O.

(3) When PJ.6 is configured in bypass mode, PJ.7 is configured as general-purpose I/O.

5.11.24.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger

Figure 5-14 shows the port diagram. summarizes the selection of the pin function.

NOTE:

Functional representation only.

Figure 5-14 Port PJ (PJ.0 to PJ.3) Diagram

Port PJ (PJ.0 to PJ.3) Pin Functions

PIN NAME (PJ.x)	x	FUNCTION	CONTROL BITS OR SIGNALS⁽¹⁾
PIN NAME (PJ.x)	x	FUNCTION	PJDIR.x	PJSEL1.x	PJSEL0.x
PJ.0/TDO/TB0OUTH/ SMCLK/SRSCG1	0	PJ.0 (I/O) ⁽²⁾	I: 0; O: 1	0	0
		TDO ⁽³⁾	X	X	X
		TB0OUTH	0	0	1
		SMCLK⁽⁵⁾	1	0	1
		N/A	0	1	0
		CPU Status Register Bit SCG1	1	1	0
		N/A	0	1	1
		Internally tied to DVSS	1	1	1
PJ.1/TDI/TCLK/ MCLK/SRSCG0	1	PJ.1 (I/O) ⁽²⁾	I: 0; O: 1	0	0
		TDI/TCLK ⁽³⁾ ⁽⁴⁾	X	X	X
		N/A	0	0	1
		MCLK	1	0	1
		N/A	0	1	0
		CPU Status Register Bit SCG0	1	1	0
		N/A	0	1	1
		Internally tied to DVSS	1	1	1
PJ.2/TMS/ACLK/ SROSCOFF	2	PJ.2 (I/O) ⁽²⁾	I: 0; O: 1	0	0
		TMS ⁽³⁾ ⁽⁴⁾	X	X	X
		N/A	0	0	1
		ACLK	1	0	1
		N/A	0	1	0
		CPU Status Register Bit OSCOFF	1	1	0
		N/A	0	1	1
		Internally tied to DVSS	1	1	1
PJ.3/TCK/COUT/ SRCPUOFF	3	PJ.3 (I/O) ⁽²⁾	I: 0; O: 1	0	0
		TCK ⁽³⁾ ⁽⁴⁾	X	X	X
		N/A	0	0	1
		COUT	1	0	1
		N/A	0	1	0
		CPU Status Register Bit CPUOFF	1	1	0
		N/A	0	1	1
		Internally tied to DVSS	1	1	1

(1) X = Don't care

(2) Default condition

(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made through the SYS module or by the Spy-Bi-Wire 4-wire entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPD.x bits have an effect in these cases.

(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.

(5) Do not use this pin as SMCLK output if the TB0OUTH functionality is used on any other pin. Select an alternative SMCLK output pin.

5.12 Device Descriptors (TLV)

Table 5-20 summarizes the Device IDs. Table 5-21 lists the contents of the device descriptor tag-length-value (TLV) structure for each device type.

Table 5-20 Device ID

DEVICE	DEVICE ID
DEVICE	01A05h	01A04h
MSP430FR5989	081h	0ABh

Table 5-21 Device Descriptor Table ⁽¹⁾

DESCRIPTION		MSP430FRxxxx (UART BSL)		MSP430FRxxxx1 (I²C BSL)
DESCRIPTION		ADDRESS	VALUE	ADDRESS	VALUE
Info Block	Info length	01A00h	06h	01A00h	06h
	CRC length	01A01h	06h	01A01h	06h
	CRC value	01A02h	Per unit	01A02h	Per unit
	CRC value	01A03h	Per unit	01A03h	Per unit
	Device ID	01A04h	See .	01A04h	See .
	Device ID	01A05h	See .	01A05h	See .
	Hardware revision	01A06h	Per unit	01A06h	Per unit
	Firmware revision	01A07h	Per unit	01A07h	Per unit
Die Record	Die record tag	01A08h	08h	01A08h	08h
	Die record length	01A09h	0Ah	01A09h	0Ah
	Lot/wafer ID	01A0Ah	Per unit	01A0Ah	Per unit
		01A0Bh	Per unit	01A0Bh	Per unit
		01A0Ch	Per unit	01A0Ch	Per unit
		01A0Dh	Per unit	01A0Dh	Per unit
	Die X position	01A0Eh	Per unit	01A0Eh	Per unit
	Die X position	01A0Fh	Per unit	01A0Fh	Per unit
	Die Y position	01A10h	Per unit	01A10h	Per unit
	Die Y position	01A11h	Per unit	01A11h	Per unit
	Test results	01A12h	Per unit	01A12h	Per unit
	Test results	01A13h	Per unit	01A13h	Per unit
ADC12B Calibration	ADC12B calibration tag	01A14h	11h	01A14h	11h
	ADC12B calibration length	01A15h	10h	01A15h	10h
	ADC gain factor⁽²⁾	01A16h	Per unit	01A16h	Per unit
	ADC gain factor⁽²⁾	01A17h	Per unit	01A17h	Per unit
	ADC offset⁽³⁾	01A18h	Per unit	01A18h	Per unit
	ADC offset⁽³⁾	01A19h	Per unit	01A19h	Per unit
	ADC 1.2-V reference Temperature sensor 30°C	01A1Ah	Per unit	01A1Ah	Per unit
	ADC 1.2-V reference Temperature sensor 30°C	01A1Bh	Per unit	01A1Bh	Per unit
	ADC 1.2-V reference Temperature sensor 95°C	01A1Ch	Per unit	01A1Ch	Per unit
	ADC 1.2-V reference Temperature sensor 95°C	01A1Dh	Per unit	01A1Dh	Per unit
	ADC 2.0-V reference Temperature sensor 30°C	01A1Eh	Per unit	01A1Eh	Per unit
	ADC 2.0-V reference Temperature sensor 30°C	01A1Fh	Per unit	01A1Fh	Per unit
	ADC 2.0-V reference Temperature sensor 95°C	01A20h	Per unit	01A20h	Per unit
	ADC 2.0-V reference Temperature sensor 95°C	01A21h	Per unit	01A21h	Per unit
	ADC 2.5-V reference Temperature sensor 30°C	01A22h	Per unit	01A22h	Per unit
	ADC 2.5-V reference Temperature sensor 30°C	01A23h	Per unit	01A23h	Per unit
	ADC 2.5-V reference Temperature sensor 95°C	01A24h	Per unit	01A24h	Per unit
	ADC 2.5-V reference Temperature sensor 95°C	01A25h	Per unit	01A25h	Per unit
REF Calibration	REF calibration tag	01A26h	12h	01A26h	12h
	REF calibration length	01A27h	06h	01A27h	06h
	REF 1.2-V reference	01A28h	Per unit	01A28h	Per unit
	REF 1.2-V reference	01A29h	Per unit	01A29h	Per unit
	REF 2.0-V reference	01A2Ah	Per unit	01A2Ah	Per unit
	REF 2.0-V reference	01A2Bh	Per unit	01A2Bh	Per unit
	REF 2.5-V reference	01A2Ch	Per unit	01A2Ch	Per unit
	REF 2.5-V reference	01A2Dh	Per unit	01A2Dh	Per unit
Random Number	128-bit random number tag	01A2Eh	15h	01A2Eh	15h
	Random number length	01A2Fh	10h	01A2Fh	10h
	128-bit random number⁽⁴⁾	01A30h	Per unit	01A30h	Per unit
		01A31h	Per unit	01A31h	Per unit
		01A32h	Per unit	01A32h	Per unit
		01A33h	Per unit	01A33h	Per unit
		01A34h	Per unit	01A34h	Per unit
		01A35h	Per unit	01A35h	Per unit
		01A36h	Per unit	01A36h	Per unit
		01A37h	Per unit	01A37h	Per unit
		01A38h	Per unit	01A38h	Per unit
		01A39h	Per unit	01A39h	Per unit
		01A3Ah	Per unit	01A3Ah	Per unit
		01A3Bh	Per unit	01A3Bh	Per unit
		01A3Ch	Per unit	01A3Ch	Per unit
		01A3Dh	Per unit	01A3Dh	Per unit
		01A3Eh	Per unit	01A3Eh	Per unit
		01A3Fh	Per unit	01A3Fh	Per unit
BSL Configuration	BSL tag	01A40h	1Ch	01A40h	1Ch
	BSL length	01A41h	02h	01A41h	02h
	BSL interface	01A42h	00h	01A42h	01h
	BSL interface configuration	01A43h	00h	01A43h	48h

(1) NA = Not applicable, Per unit = Content can differ from device to device

(2) ADC gain: The gain correction factor is measured using the internal voltage reference with REFOUT = 0. Other settings (for example, with REFOUT = 1) can result in different correction factors.

(3) ADC offset: The offset correction factor is measured using the internal 2.5-V reference.

(4) 128-bit random number: The random number is generated during production test using the CryptGenRandom() function from Microsoft®.

5.13 Memory

Table 5-22 summarizes the memory map.

Table 5-22 Memory Organization⁽¹⁾

		MSP430FRxxx9(1)
Memory (FRAM) Main: interrupt vectors and signatures Main: code memory	Total Size	127KB 00FFFFh–00FF80h 023FFFh–004400h
RAM	Sect 1	2KB 0023FFh–001C00h
Boot memory (ROM)		256 B 001BFFh–001B00h
Device Descriptor Info (TLV)		256 B 001AFFh–001A00h
Information memory (FRAM)	Info A	128 B 0019FFh–001980h
	Info B	128 B 00197Fh–001900h
	Info C	128 B 0018FFh–001880h
	Info D	128 B 00187Fh–001800h
Bootloader (BSL) memory (ROM)	BSL 3	512 B 0017FFh–001600h
	BSL 2	512 B 0015FFh–001400h
	BSL 1	512 B 0013FFh–001200h
	BSL 0	512 B 0011FFh–001000h
Peripherals	Size	4KB 000FFFh–000020h
Tiny RAM	Size	26 B 000001Fh–000006h
Reserved (ROM)	Size	6 B 000005h–000000h

(1) All address space not listed is considered vacant memory.

5.13.1 Peripheral File Map

Table 5-23 lists the base address for each available peripheral. Table 5-24 through Table 5-59 list the registers and their offsets for each peripheral.

Table 5-23 Peripherals

MODULE NAME	BASE ADDRESS	OFFSET ADDRESS RANGE
Special Functions (see Table 5-24)	0100h	000h–01Fh
PMM (see Table 5-25)	0120h	000h–01Fh
FRAM Control (see Table 5-26)	0140h	000h–00Fh
CRC16 (see Table 5-27)	0150h	000h–007h
RAM Controller (see Table 5-28)	0158h	000h–001h
Watchdog Timer (see Table 5-29)	015Ch	000h–001h
CS (see Table 5-30)	0160h	000h–00Fh
SYS (see Table 5-31)	0180h	000h–01Fh
Shared Reference (see Table 5-32)	01B0h	000h–001h
Port P1, P2 (see Table 5-33)	0200h	000h–01Fh
Port P3, P4 (see Table 5-34)	0220h	000h–01Fh
Port P5, P6 (see Table 5-35)	0240h	000h–01Fh
Port P7, P8 (see Table 5-36)	0260h	000h–01Fh
Port P9, P10 (see Table 5-37)	0280h	000h–01Fh
Port PJ (see Table 5-38)	0320h	000h–01Fh
Timer_A TA0 (see Table 5-39)	0340h	000h–02Fh
Timer_A TA1 (see Table 5-40)	0380h	000h–02Fh
Timer_B TB0 (see Table 5-41)	03C0h	000h–02Fh
Timer_A TA2 (see Table 5-42)	0400h	000h–02Fh
Capacitive Touch I/O 0 (see Table 5-43)	0430h	000h–00Fh
Timer_A TA3 (see Table 5-44)	0440h	000h–02Fh
Capacitive Touch I/O 1 (see Table 5-45)	0470h	000h–00Fh
Real-Time Clock (RTC_C) (see Table 5-46)	04A0h	000h–01Fh
32-Bit Hardware Multiplier (see Table 5-47)	04C0h	000h–02Fh
DMA General Control (see Table 5-48)	0500h	000h–00Fh
DMA Channel 0 (see Table 5-48)	0510h	000h–00Fh
DMA Channel 1 (see Table 5-48)	0520h	000h–00Fh
DMA Channel 2 (see Table 5-48)	0530h	000h–00Fh
MPU (see Table 5-49)	05A0h	000h–00Fh
eUSCI_A0 (see Table 5-50)	05C0h	000h–01Fh
eUSCI_A1 (see Table 5-51)	05E0h	000h–01Fh
eUSCI_B0 (see Table 5-52)	0640h	000h–02Fh
eUSCI_B1 (see Table 5-53)	0680h	000h–02Fh
ADC12_B (see Table 5-54)	0800h	000h–09Fh
Comparator_E (see Table 5-55)	08C0h	000h–00Fh
CRC32 (see Table 5-56)	0980h	000h–02Fh
AES (see Table 5-57)	09C0h	000h–00Fh
LCD_C (see Table 5-58)	0A00h	000h–05Fh
ESI (see Table 5-59)	0D00h	000h–09Fh
ESI RAM (128 bytes)	0E00h	00h–07Fh

Table 5-24 Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION	REGISTER	OFFSET
SFR interrupt enable	SFRIE1	00h
SFR interrupt flag	SFRIFG1	02h
SFR reset pin control	SFRRPCR	04h

Table 5-25 PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION	REGISTER	OFFSET
PMM control 0	PMMCTL0	00h
PMM interrupt flags	PMMIFG	0Ah
PM5 control 0	PM5CTL0	10h

Table 5-26 FRAM Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION	REGISTER	OFFSET
FRAM control 0	FRCTL0	00h
General control 0	GCCTL0	04h
General control 1	GCCTL1	06h

Table 5-27 CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION	REGISTER	OFFSET
CRC data input	CRC16DI	00h
CRC data input reverse byte	CRCDIRB	02h
CRC initialization and result	CRCINIRES	04h
CRC result reverse byte	CRCRESR	06h

Table 5-28 RAM Controller Registers (Base Address: 0158h)

REGISTER DESCRIPTION	REGISTER	OFFSET
RAM controller control 0	RCCTL0	00h

Table 5-29 Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION	REGISTER	OFFSET
Watchdog timer control	WDTCTL	00h

Table 5-30 CS Registers (Base Address: 0160h)

REGISTER DESCRIPTION	REGISTER	OFFSET
CS control 0	CSCTL0	00h
CS control 1	CSCTL1	02h
CS control 2	CSCTL2	04h
CS control 3	CSCTL3	06h
CS control 4	CSCTL4	08h
CS control 5	CSCTL5	0Ah
CS control 6	CSCTL6	0Ch

Table 5-31 SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION	REGISTER	OFFSET
System control	SYSCTL	00h
JTAG mailbox control	SYSJMBC	06h
JTAG mailbox input 0	SYSJMBI0	08h
JTAG mailbox input 1	SYSJMBI1	0Ah
JTAG mailbox output 0	SYSJMBO0	0Ch
JTAG mailbox output 1	SYSJMBO1	0Eh
User NMI vector generator	SYSUNIV	1Ah
System NMI vector generator	SYSSNIV	1Ch
Reset vector generator	SYSRSTIV	1Eh

Table 5-32 Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Shared reference control	REFCTL	00h

Table 5-33 Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P1 input	P1IN	00h
Port P1 output	P1OUT	02h
Port P1 direction	P1DIR	04h
Port P1 resistor enable	P1REN	06h
Port P1 selection 0	P1SEL0	0Ah
Port P1 selection 1	P1SEL1	0Ch
Port P1 interrupt vector word	P1IV	0Eh
Port P1 complement selection	P1SELC	16h
Port P1 interrupt edge select	P1IES	18h
Port P1 interrupt enable	P1IE	1Ah
Port P1 interrupt flag	P1IFG	1Ch
Port P2 input	P2IN	01h
Port P2 output	P2OUT	03h
Port P2 direction	P2DIR	05h
Port P2 resistor enable	P2REN	07h
Port P2 selection 0	P2SEL0	0Bh
Port P2 selection 1	P2SEL1	0Dh
Port P2 complement selection	P2SELC	17h
Port P2 interrupt vector word	P2IV	1Eh
Port P2 interrupt edge select	P2IES	19h
Port P2 interrupt enable	P2IE	1Bh
Port P2 interrupt flag	P2IFG	1Dh

Table 5-34 Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P3 input	P3IN	00h
Port P3 output	P3OUT	02h
Port P3 direction	P3DIR	04h
Port P3 resistor enable	P3REN	06h
Port P3 selection 0	P3SEL0	0Ah
Port P3 selection 1	P3SEL1	0Ch
Port P3 interrupt vector word	P3IV	0Eh
Port P3 complement selection	P3SELC	16h
Port P3 interrupt edge select	P3IES	18h
Port P3 interrupt enable	P3IE	1Ah
Port P3 interrupt flag	P3IFG	1Ch
Port P4 input	P4IN	01h
Port P4 output	P4OUT	03h
Port P4 direction	P4DIR	05h
Port P4 resistor enable	P4REN	07h
Port P4 selection 0	P4SEL0	0Bh
Port P4 selection 1	P4SEL1	0Dh
Port P4 complement selection	P4SELC	17h
Port P4 interrupt vector word	P4IV	1Eh
Port P4 interrupt edge select	P4IES	19h
Port P4 interrupt enable	P4IE	1Bh
Port P4 interrupt flag	P4IFG	1Dh

Table 5-35 Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P5 input	P5IN	00h
Port P5 output	P5OUT	02h
Port P5 direction	P5DIR	04h
Port P5 resistor enable	P5REN	06h
Port P5 selection 0	P5SEL0	0Ah
Port P5 selection 1	P5SEL1	0Ch
Reserved		0Eh
Port P5 complement selection	P5SELC	16h
Reserved		18h
Reserved		1Ah
Reserved		1Ch
Port P6 input	P6IN	01h
Port P6 output	P6OUT	03h
Port P6 direction	P6DIR	05h
Port P6 resistor enable	P6REN	07h
Port P6 selection 0	P6SEL0	0Bh
Port P6 selection 1	P6SEL1	0Dh
Port P6 complement selection	P6SELC	17h
Reserved		1Eh
Reserved		19h
Reserved		1Bh
Reserved		1Dh

Table 5-36 Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P7 input	P7IN	00h
Port P7 output	P7OUT	02h
Port P7 direction	P7DIR	04h
Port P7 resistor enable	P7REN	06h
Port P7 selection 0	P7SEL0	0Ah
Port P7 selection 1	P7SEL1	0Ch
Reserved		0Eh
Port P7 complement selection	P7SELC	16h
Reserved		18h
Reserved		1Ah
Reserved		1Ch
Port P8 input	P8IN	01h
Port P8 output	P8OUT	03h
Port P8 direction	P8DIR	05h
Port P8 resistor enable	P8REN	07h
Port P8 selection 0	P8SEL0	0Bh
Port P8 selection 1	P8SEL1	0Dh
Port P8 complement selection	P8SELC	17h
Reserved		1Eh
Reserved		19h
Reserved		1Bh
Reserved		1Dh

Table 5-37 Port P9, P10 Registers (Base Address: 0280h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P9 input	P9IN	00h
Port P9 output	P9OUT	02h
Port P9 direction	P9DIR	04h
Port P9 resistor enable	P9REN	06h
Port P9 selection 0	P9SEL0	0Ah
Port P9 selection 1	P9SEL1	0Ch
Reserved		0Eh
Port P9 complement selection	P9SELC	16h
Reserved		18h
Reserved		1Ah
Reserved		1Ch
Port P10 input	P10IN	01h
Port P10 output	P10OUT	03h
Port P10 direction	P10DIR	05h
Port P10 resistor enable	P10REN	07h
Port P10 selection 0	P10SEL0	0Bh
Port P10 selection 1	P10SEL1	0Dh
Port P10 complement selection	P10SELC	17h
Reserved		1Eh
Reserved		19h
Reserved		1Bh
Reserved		1Dh

Table 5-38 Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port PJ input	PJIN	00h
Port PJ output	PJOUT	02h
Port PJ direction	PJDIR	04h
Port PJ resistor enable	PJREN	06h
Port PJ selection 0	PJSEL0	0Ah
Port PJ selection 1	PJSEL1	0Ch
Port PJ complement selection	PJSELC	16h

Table 5-39 Timer_A TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION	REGISTER	OFFSET
TA0 control	TA0CTL	00h
Capture/compare control 0	TA0CCTL0	02h
Capture/compare control 1	TA0CCTL1	04h
Capture/compare control 2	TA0CCTL2	06h
Capture/compare control 3	TA0CCTL3	08h
Capture/compare control 4	TA0CCTL4	0Ah
TA0 counter	TA0R	10h
Capture/compare 0	TA0CCR0	12h
Capture/compare 1	TA0CCR1	14h
Capture/compare 2	TA0CCR2	16h
Capture/compare 3	TA0CCR3	18h
Capture/compare 4	TA0CCR4	1Ah
TA0 expansion 0	TA0EX0	20h
TA0 interrupt vector	TA0IV	2Eh

Table 5-40 Timer_A TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION	REGISTER	OFFSET
TA1 control	TA1CTL	00h
Capture/compare control 0	TA1CCTL0	02h
Capture/compare control 1	TA1CCTL1	04h
Capture/compare control 2	TA1CCTL2	06h
TA1 counter	TA1R	10h
Capture/compare 0	TA1CCR0	12h
Capture/compare 1	TA1CCR1	14h
Capture/compare 2	TA1CCR2	16h
TA1 expansion 0	TA1EX0	20h
TA1 interrupt vector	TA1IV	2Eh

Table 5-41 Timer_B TB0 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
TB0 control	TB0CTL	00h
Capture/compare control 0	TB0CCTL0	02h
Capture/compare control 1	TB0CCTL1	04h
Capture/compare control 2	TB0CCTL2	06h
Capture/compare control 3	TB0CCTL3	08h
Capture/compare control 4	TB0CCTL4	0Ah
Capture/compare control 5	TB0CCTL5	0Ch
Capture/compare control 6	TB0CCTL6	0Eh
TB0 counter	TB0R	10h
Capture/compare 0	TB0CCR0	12h
Capture/compare 1	TB0CCR1	14h
Capture/compare 2	TB0CCR2	16h
Capture/compare 3	TB0CCR3	18h
Capture/compare 4	TB0CCR4	1Ah
Capture/compare 5	TB0CCR5	1Ch
Capture/compare 6	TB0CCR6	1Eh
TB0 expansion 0	TB0EX0	20h
TB0 interrupt vector	TB0IV	2Eh

Table 5-42 Timer_A TA2 Registers (Base Address: 0400h)

REGISTER DESCRIPTION	REGISTER	OFFSET
TA2 control	TA2CTL	00h
Capture/compare control 0	TA2CCTL0	02h
Capture/compare control 1	TA2CCTL1	04h
TA2 counter	TA2R	10h
Capture/compare 0	TA2CCR0	12h
Capture/compare 1	TA2CCR1	14h
TA2 expansion 0	TA2EX0	20h
TA2 interrupt vector	TA2IV	2Eh

Table 5-43 Capacitive Touch I/O 0 Registers (Base Address: 0430h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Capacitive Touch I/O 0 control	CAPTIO0CTL	0Eh

Table 5-44 Timer_A TA3 Registers (Base Address: 0440h)

REGISTER DESCRIPTION	REGISTER	OFFSET
TA3 control	TA3CTL	00h
Capture/compare control 0	TA3CCTL0	02h
Capture/compare control 1	TA3CCTL1	04h
Capture/compare control 2	TA3CCTL2	06h
Capture/compare control 3	TA3CCTL3	08h
Capture/compare control 4	TA3CCTL4	0Ah
TA3 counter	TA3R	10h
Capture/compare 0	TA3CCR0	12h
Capture/compare 1	TA3CCR1	14h
Capture/compare 2	TA3CCR2	16h
Capture/compare 3	TA3CCR3	18h
Capture/compare 4	TA3CCR4	1Ah
TA3 expansion 0	TA3EX0	20h
TA3 interrupt vector	TA3IV	2Eh

Table 5-45 Capacitive Touch I/O 1 Registers (Base Address: 0470h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Capacitive Touch I/O 1 control	CAPTIO1CTL	0Eh

Table 5-46 RTC_C Registers (Base Address: 04A0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
RTC control 0	RTCCTL0	00h
RTC password	RTCPWD	01h
RTC control 1	RTCCTL1	02h
RTC control 3	RTCCTL3	03h
RTC offset calibration	RTCOCAL	04h
RTC temperature compensation	RTCTCMP	06h
RTC prescaler 0 control	RTCPS0CTL	08h
RTC prescaler 1 control	RTCPS1CTL	0Ah
RTC prescaler 0	RTCPS0	0Ch
RTC prescaler 1	RTCPS1	0Dh
RTC interrupt vector word	RTCIV	0Eh
RTC seconds/counter 1	RTCSEC/RTCNT1	10h
RTC minutes/counter 2	RTCMIN/RTCNT2	11h
RTC hours/counter 3	RTCHOUR/RTCNT3	12h
RTC day of week/counter 4	RTCDOW/RTCNT4	13h
RTC days	RTCDAY	14h
RTC month	RTCMON	15h
RTC year	RTCYEAR	16h
RTC alarm minutes	RTCAMIN	18h
RTC alarm hours	RTCAHOUR	19h
RTC alarm day of week	RTCADOW	1Ah
RTC alarm days	RTCADAY	1Bh
Binary-to-BCD conversion	BIN2BCD	1Ch
BCD-to-Binary conversion	BCD2BIN	1Eh

Table 5-47 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
16-bit operand 1 – multiply	MPY	00h
16-bit operand 1 – signed multiply	MPYS	02h
16-bit operand 1 – multiply accumulate	MAC	04h
16-bit operand 1 – signed multiply accumulate	MACS	06h
16-bit operand 2	OP2	08h
16 × 16 result low word	RESLO	0Ah
16 × 16 result high word	RESHI	0Ch
16 × 16 sum extension	SUMEXT	0Eh
32-bit operand 1 – multiply low word	MPY32L	10h
32-bit operand 1 – multiply high word	MPY32H	12h
32-bit operand 1 – signed multiply low word	MPYS32L	14h
32-bit operand 1 – signed multiply high word	MPYS32H	16h
32-bit operand 1 – multiply accumulate low word	MAC32L	18h
32-bit operand 1 – multiply accumulate high word	MAC32H	1Ah
32-bit operand 1 – signed multiply accumulate low word	MACS32L	1Ch
32-bit operand 1 – signed multiply accumulate high word	MACS32H	1Eh
32-bit operand 2 – low word	OP2L	20h
32-bit operand 2 – high word	OP2H	22h
32 × 32 result 0 – least significant word	RES0	24h
32 × 32 result 1	RES1	26h
32 × 32 result 2	RES2	28h
32 × 32 result 3 – most significant word	RES3	2Ah
MPY32 control 0	MPY32CTL0	2Ch

Table 5-48 DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)

REGISTER DESCRIPTION	REGISTER	OFFSET
DMA channel 0 control	DMA0CTL	00h
DMA channel 0 source address low	DMA0SAL	02h
DMA channel 0 source address high	DMA0SAH	04h
DMA channel 0 destination address low	DMA0DAL	06h
DMA channel 0 destination address high	DMA0DAH	08h
DMA channel 0 transfer size	DMA0SZ	0Ah
DMA channel 1 control	DMA1CTL	00h
DMA channel 1 source address low	DMA1SAL	02h
DMA channel 1 source address high	DMA1SAH	04h
DMA channel 1 destination address low	DMA1DAL	06h
DMA channel 1 destination address high	DMA1DAH	08h
DMA channel 1 transfer size	DMA1SZ	0Ah
DMA channel 2 control	DMA2CTL	00h
DMA channel 2 source address low	DMA2SAL	02h
DMA channel 2 source address high	DMA2SAH	04h
DMA channel 2 destination address low	DMA2DAL	06h
DMA channel 2 destination address high	DMA2DAH	08h
DMA channel 2 transfer size	DMA2SZ	0Ah
DMA module control 0	DMACTL0	00h
DMA module control 1	DMACTL1	02h
DMA module control 2	DMACTL2	04h
DMA module control 3	DMACTL3	06h
DMA module control 4	DMACTL4	08h
DMA interrupt vector	DMAIV	0Eh

Table 5-49 MPU Control Registers (Base Address: 05A0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
MPU control 0	MPUCTL0	00h
MPU control 1	MPUCTL1	02h
MPU segmentation border 2	MPUSEGB2	04h
MPU segmentation border 1	MPUSEGB1	06h
MPU access management	MPUSAM	08h
MPU IP control 0	MPUIPC0	0Ah
MPU IP encapsulation segment border 2	MPUIPSEGB2	0Ch
MPU IP encapsulation segment border 1	MPUIPSEGB1	0Eh

Table 5-50 eUSCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
eUSCI_A control word 0	UCA0CTLW0	00h
eUSCI _A control word 1	UCA0CTLW1	02h
eUSCI_A baud rate 0	UCA0BR0	06h
eUSCI_A baud rate 1	UCA0BR1	07h
eUSCI_A modulation control	UCA0MCTLW	08h
eUSCI_A status word	UCA0STATW	0Ah
eUSCI_A receive buffer	UCA0RXBUF	0Ch
eUSCI_A transmit buffer	UCA0TXBUF	0Eh
eUSCI_A LIN control	UCA0ABCTL	10h
eUSCI_A IrDA transmit control	UCA0IRTCTL	12h
eUSCI_A IrDA receive control	UCA0IRRCTL	13h
eUSCI_A interrupt enable	UCA0IE	1Ah
eUSCI_A interrupt flags	UCA0IFG	1Ch
eUSCI_A interrupt vector word	UCA0IV	1Eh

Table 5-51 eUSCI_A1 Registers (Base Address:05E0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
eUSCI_A control word 0	UCA1CTLW0	00h
eUSCI _A control word 1	UCA1CTLW1	02h
eUSCI_A baud rate 0	UCA1BR0	06h
eUSCI_A baud rate 1	UCA1BR1	07h
eUSCI_A modulation control	UCA1MCTLW	08h
eUSCI_A status word	UCA1STATW	0Ah
eUSCI_A receive buffer	UCA1RXBUF	0Ch
eUSCI_A transmit buffer	UCA1TXBUF	0Eh
eUSCI_A LIN control	UCA1ABCTL	10h
eUSCI_A IrDA transmit control	UCA1IRTCTL	12h
eUSCI_A IrDA receive control	UCA1IRRCTL	13h
eUSCI_A interrupt enable	UCA1IE	1Ah
eUSCI_A interrupt flags	UCA1IFG	1Ch
eUSCI_A interrupt vector word	UCA1IV	1Eh

Table 5-52 eUSCI_B0 Registers (Base Address: 0640h)

REGISTER DESCRIPTION	REGISTER	OFFSET
eUSCI_B control word 0	UCB0CTLW0	00h
eUSCI_B control word 1	UCB0CTLW1	02h
eUSCI_B bit rate 0	UCB0BR0	06h
eUSCI_B bit rate 1	UCB0BR1	07h
eUSCI_B status word	UCB0STATW	08h
eUSCI_B byte counter threshold	UCB0TBCNT	0Ah
eUSCI_B receive buffer	UCB0RXBUF	0Ch
eUSCI_B transmit buffer	UCB0TXBUF	0Eh
eUSCI_B I2C own address 0	UCB0I2COA0	14h
eUSCI_B I2C own address 1	UCB0I2COA1	16h
eUSCI_B I2C own address 2	UCB0I2COA2	18h
eUSCI_B I2C own address 3	UCB0I2COA3	1Ah
eUSCI_B received address	UCB0ADDRX	1Ch
eUSCI_B address mask	UCB0ADDMASK	1Eh
eUSCI_B I2C slave address	UCB0I2CSA	20h
eUSCI_B interrupt enable	UCB0IE	2Ah
eUSCI_B interrupt flags	UCB0IFG	2Ch
eUSCI_B interrupt vector word	UCB0IV	2Eh

Table 5-53 eUSCI_B1 Registers (Base Address: 0680h)

REGISTER DESCRIPTION	REGISTER	OFFSET
eUSCI_B control word 0	UCB1CTLW0	00h
eUSCI_B control word 1	UCB1CTLW1	02h
eUSCI_B bit rate 0	UCB1BR0	06h
eUSCI_B bit rate 1	UCB1BR1	07h
eUSCI_B status word	UCB1STATW	08h
eUSCI_B byte counter threshold	UCB1TBCNT	0Ah
eUSCI_B receive buffer	UCB1RXBUF	0Ch
eUSCI_B transmit buffer	UCB1TXBUF	0Eh
eUSCI_B I2C own address 0	UCB1I2COA0	14h
eUSCI_B I2C own address 1	UCB1I2COA1	16h
eUSCI_B I2C own address 2	UCB1I2COA2	18h
eUSCI_B I2C own address 3	UCB1I2COA3	1Ah
eUSCI_B received address	UCB1ADDRX	1Ch
eUSCI_B address mask	UCB1ADDMASK	1Eh
eUSCI_B I2C slave address	UCB1I2CSA	20h
eUSCI_B interrupt enable	UCB1IE	2Ah
eUSCI_B interrupt flags	UCB1IFG	2Ch
eUSCI_B interrupt vector word	UCB1IV	2Eh

Table 5-54 ADC12_B Registers (Base Address: 0800h)

REGISTER DESCRIPTION	REGISTER	OFFSET
ADC12_B control 0	ADC12CTL0	00h
ADC12_B control 1	ADC12CTL1	02h
ADC12_B control 2	ADC12CTL2	04h
ADC12_B control 3	ADC12CTL3	06h
ADC12_B window comparator low threshold	ADC12LO	08h
ADC12_B window comparator high threshold	ADC12HI	0Ah
ADC12_B interrupt flag 0	ADC12IFGR0	0Ch
ADC12_B Interrupt flag 1	ADC12IFGR1	0Eh
ADC12_B interrupt flag 2	ADC12IFGR2	10h
ADC12_B interrupt enable 0	ADC12IER0	12h
ADC12_B interrupt enable 1	ADC12IER1	14h
ADC12_B interrupt enable 2	ADC12IER2	16h
ADC12_B interrupt vector	ADC12IV	18h
ADC12_B memory control 0	ADC12MCTL0	20h
ADC12_B memory control 1	ADC12MCTL1	22h
ADC12_B memory control 2	ADC12MCTL2	24h
ADC12_B memory control 3	ADC12MCTL3	26h
ADC12_B memory control 4	ADC12MCTL4	28h
ADC12_B memory control 5	ADC12MCTL5	2Ah
ADC12_B memory control 6	ADC12MCTL6	2Ch
ADC12_B memory control 7	ADC12MCTL7	2Eh
ADC12_B memory control 8	ADC12MCTL8	30h
ADC12_B memory control 9	ADC12MCTL9	32h
ADC12_B memory control 10	ADC12MCTL10	34h
ADC12_B memory control 11	ADC12MCTL11	36h
ADC12_B memory control 12	ADC12MCTL12	38h
ADC12_B memory control 13	ADC12MCTL13	3Ah
ADC12_B memory control 14	ADC12MCTL14	3Ch
ADC12_B memory control 15	ADC12MCTL15	3Eh
ADC12_B memory control 16	ADC12MCTL16	40h
ADC12_B memory control 17	ADC12MCTL17	42h
ADC12_B memory control 18	ADC12MCTL18	44h
ADC12_B memory control 19	ADC12MCTL19	46h
ADC12_B memory control 20	ADC12MCTL20	48h
ADC12_B memory control 21	ADC12MCTL21	4Ah
ADC12_B memory control 22	ADC12MCTL22	4Ch
ADC12_B memory control 23	ADC12MCTL23	4Eh
ADC12_B memory control 24	ADC12MCTL24	50h
ADC12_B memory control 25	ADC12MCTL25	52h
ADC12_B memory control 26	ADC12MCTL26	54h
ADC12_B memory control 27	ADC12MCTL27	56h
ADC12_B memory control 28	ADC12MCTL28	58h
ADC12_B memory control 29	ADC12MCTL29	5Ah
ADC12_B memory control 30	ADC12MCTL30	5Ch
ADC12_B memory control 31	ADC12MCTL31	5Eh
ADC12_B memory 0	ADC12MEM0	60h
ADC12_B memory 1	ADC12MEM1	62h
ADC12_B memory 2	ADC12MEM2	64h
ADC12_B memory 3	ADC12MEM3	66h
ADC12_B memory 4	ADC12MEM4	68h
ADC12_B memory 5	ADC12MEM5	6Ah
ADC12_B memory 6	ADC12MEM6	6Ch
ADC12_B memory 7	ADC12MEM7	6Eh
ADC12_B memory 8	ADC12MEM8	70h
ADC12_B memory 9	ADC12MEM9	72h
ADC12_B memory 10	ADC12MEM10	74h
ADC12_B memory 11	ADC12MEM11	76h
ADC12_B memory 12	ADC12MEM12	78h
ADC12_B memory 13	ADC12MEM13	7Ah
ADC12_B memory 14	ADC12MEM14	7Ch
ADC12_B memory 15	ADC12MEM15	7Eh
ADC12_B memory 16	ADC12MEM16	80h
ADC12_B memory 17	ADC12MEM17	82h
ADC12_B memory 18	ADC12MEM18	84h
ADC12_B memory 19	ADC12MEM19	86h
ADC12_B memory 20	ADC12MEM20	88h
ADC12_B memory 21	ADC12MEM21	8Ah
ADC12_B memory 22	ADC12MEM22	8Ch
ADC12_B memory 23	ADC12MEM23	8Eh
ADC12_B memory 24	ADC12MEM24	90h
ADC12_B memory 25	ADC12MEM25	92h
ADC12_B memory 26	ADC12MEM26	94h
ADC12_B memory 27	ADC12MEM27	96h
ADC12_B memory 28	ADC12MEM28	98h
ADC12_B memory 29	ADC12MEM29	9Ah
ADC12_B memory 30	ADC12MEM30	9Ch
ADC12_B memory 31	ADC12MEM31	9Eh

Table 5-55 Comparator_E Registers (Base Address: 08C0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Comparator control 0	CECTL0	00h
Comparator control 1	CECTL1	02h
Comparator control 2	CECTL2	04h
Comparator control 3	CECTL3	06h
Comparator interrupt	CEINT	0Ch
Comparator interrupt vector word	CEIV	0Eh

Table 5-56 CRC32 Registers (Base Address: 0980h)

REGISTER DESCRIPTION	REGISTER	OFFSET
CRC32 data input	CRC32DIW0	00h
Reserved		02h
Reserved		04h
CRC32 data input reverse	CRC32DIRBW0	06h
CRC32 initialization and result word 0	CRC32INIRESW0	08h
CRC32 initialization and result word 1	CRC32INIRESW1	0Ah
CRC32 result reverse word 1	CRC32RESRW1	0Ch
CRC32 result reverse word 0	CRC32RESRW1	0Eh
CRC16 data input	CRC16DIW0	10h
Reserved		12h
Reserved		14h
CRC16 data input reverse	CRC16DIRBW0	16h
CRC16 initialization and result word 0	CRC16INIRESW0	18h
Reserved		1Ah
Reserved		1Ch
CRC16 result reverse word 0	CRC16RESRW1	1Eh
Reserved		20h
Reserved		22h
Reserved		24h
Reserved		26h
Reserved		28h
Reserved		2Ah
Reserved		2Ch
Reserved		2Eh

Table 5-57 AES Accelerator Registers (Base Address: 09C0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
AES accelerator control 0	AESACTL0	00h
AES accelerator control 1	AESACTL1	02h
AES accelerator status	AESASTAT	04h
AES accelerator key	AESAKEY	06h
AES accelerator data in	AESADIN	008h
AES accelerator data out	AESADOUT	00Ah
AES accelerator XORed data in	AESAXDIN	00Ch
AES accelerator XORed data in (no trigger)	AESAXIN	00Eh

Table 5-58 LCD_C Registers (Base Address: 0A00h)

REGISTER DESCRIPTION	REGISTER	OFFSET
LCD_C control 0	LCDCCTL0	000h
LCD_C control 1	LCDCCTL1	002h
LCD_C blinking control	LCDCBLKCTL	004h
LCD_C memory control	LCDCMEMCTL	006h
LCD_C voltage control	LCDCVCTL	008h
LCD_C port control 0	LCDCPCTL0	00Ah
LCD_C port control 1	LCDCPCTL1	00Ch
LCD_C port control 2	LCDCPCTL2	00Eh
LCD_C charge pump control	LCDCCPCTL	012h
LCD_C interrupt vector	LCDCIV	01Eh
Static and 2 to 4 mux modes
LCD_C memory 1	LCDM1	020h
LCD_C memory 2	LCDM2	021h
LCD_C memory 3	LCDM3	022h
LCD_C memory 4	LCDM4	023h
LCD_C memory 5	LCDM5	024h
LCD_C memory 6	LCDM6	025h
LCD_C memory 7	LCDM7	026h
LCD_C memory 8	LCDM8	027h
LCD_C memory 9	LCDM9	028h
LCD_C memory 10	LCDM10	029h
LCD_C memory 11	LCDM11	02Ah
LCD_C memory 12	LCDM12	02Bh
LCD_C memory 13	LCDM13	02Ch
LCD_C memory 14	LCDM14	02Dh
LCD_C memory 15	LCDM15	02Eh
LCD_C memory 16	LCDM16	02Fh
LCD_C memory 17	LCDM17	030h
LCD_C memory 18	LCDM18	031h
LCD_C memory 19	LCDM19	032h
LCD_C memory 20	LCDM20	033h
LCD_C memory 21	LCDM21	034h
LCD_C memory 22	LCDM22	035h
Reserved		036h
Reserved		037h
LCD_C blinking memory 1	LCDBM1	040h
LCD_C blinking memory 2	LCDBM2	041h
LCD_C blinking memory 3	LCDBM3	042h
LCD_C blinking memory 4	LCDBM4	043h
LCD_C blinking memory 5	LCDBM5	044h
LCD_C blinking memory 6	LCDBM6	045h
LCD_C blinking memory 7	LCDBM7	046h
LCD_C blinking memory 8	LCDBM8	047h
LCD_C blinking memory 9	LCDBM9	048h
LCD_C blinking memory 10	LCDBM10	049h
LCD_C blinking memory 11	LCDBM11	04Ah
LCD_C blinking memory 12	LCDBM12	04Bh
LCD_C blinking memory 13	LCDBM13	04Ch
LCD_C blinking memory 14	LCDBM14	04Dh
LCD_C blinking memory 15	LCDBM15	04Eh
LCD_C blinking memory 16	LCDBM16	04Fh
LCD_C blinking memory 17	LCDBM17	050h
LCD_C blinking memory 18	LCDBM18	051h
LCD_C blinking memory 19	LCDBM19	052h
LCD_C blinking memory 20	LCDBM20	053h
LCD_C blinking memory 21	LCDBM21	054h
LCD_C blinking memory 22	LCDBM22	055h
Reserved		056h
Reserved		057h
5 to 8 mux modes
LCD_C memory 1	LCDM1	020h
LCD_C memory 2	LCDM2	021h
LCD_C memory 3	LCDM3	022h
LCD_C memory 4	LCDM4	023h
LCD_C memory 5	LCDM5	024h
LCD_C memory 6	LCDM6	025h
LCD_C memory 7	LCDM7	026h
LCD_C memory 8	LCDM8	027h
LCD_C memory 9	LCDM9	028h
LCD_C memory 10	LCDM10	029h
LCD_C memory 11	LCDM11	02Ah
LCD_C memory 12	LCDM12	02Bh
LCD_C memory 13	LCDM13	02Ch
LCD_C memory 14	LCDM14	02Dh
LCD_C memory 15	LCDM15	02Eh
LCD_C memory 16	LCDM16	02Fh
LCD_C memory 17	LCDM17	030h
LCD_C memory 18	LCDM18	031h
LCD_C memory 19	LCDM19	032h
LCD_C memory 20	LCDM20	033h
LCD_C memory 21	LCDM21	034h
LCD_C memory 22	LCDM22	035h
LCD_C memory 23	LCDM23	036h
LCD_C memory 24	LCDM24	037h
LCD_C memory 25	LCDM25	038h
LCD_C memory 26	LCDM26	039h
LCD_C memory 27	LCDM27	03Ah
LCD_C memory 28	LCDM28	03Bh
LCD_C memory 29	LCDM29	03Ch
LCD_C memory 30	LCDM30	03Dh
LCD_C memory 31	LCDM31	03Eh
LCD_C memory 32	LCDM32	03Fh
LCD_C memory 33	LCDM33	040h
LCD_C memory 34	LCDM34	041h
LCD_C memory 35	LCDM35	042h
LCD_C memory 36	LCDM36	043h
LCD_C memory 37	LCDM37	044h
LCD_C memory 38	LCDM38	045h
LCD_C memory 39	LCDM39	046h
LCD_C memory 40	LCDM40	047h
LCD_C memory 41	LCDM41	048h
LCD_C memory 42	LCDM42	049h
LCD_C memory 43	LCDM43	04Ah

Table 5-59 Extended Scan Interface (ESI) Registers (Base Address: 0D00h)

REGISTER DESCRIPTION	REGISTER	OFFSET
ESI debug 1	ESIDEBUG1	000h
ESI debug 2	ESIDEBUG2	002h
ESI debug 3	ESIDEBUG3	004h
ESI debug 4	ESIDEBUG4	006h
ESI debug 5	ESIDEBUG5	008h
Reserved		00Ah
Reserved		00Ch
Reserved		00Eh
ESI PSM counter 0	ESICNT0	010h
ESI PSM counter 1	ESICNT1	012h
ESI PSM counter 2	ESICNT2	014h
ESI oscillator counter	ESICNT3	016h
Reserved		018h
ESI interrupt vector	ESIIV	01Ah
ESI interrupt 1	ESIINT1	01Ch
ESI interrupt 2	ESIINT2	01Eh
ESI AFE control	ESIAFE	020h
ESI PPU control	ESIPPU	022h
ESI TSM control	ESITSM	024h
ESI PSM control	ESIPSM	026h
ESI oscillator control	ESIOSC	028h
ESI control	ESICTL	02Ah
ESI PSM counter threshold 1	ESITHR1	02Ch
ESI PSM counter threshold 2	ESITHR2	02Eh
ESI A/D conversion memory 1	ESIADMEM1	030h
ESI A/D conversion memory 2	ESIADMEM2	032h
ESI A/D conversion memory 3	ESIADMEM3	034h
ESI A/D conversion memory 4	ESIADMEM4	036h
Reserved		038h
Reserved		03Ah
Reserved		03Ch
Reserved		03Eh
ESI DAC1 0	ESIDAC1R0	040h
ESI DAC1 1	ESIDAC1R1	042h
ESI DAC1 2	ESIDAC1R2	044h
ESI DAC1 3	ESIDAC1R3	046h
ESI DAC1 4	ESIDAC1R4	048h
ESI DAC1 5	ESIDAC1R5	04Ah
ESI DAC1 6	ESIDAC1R6	04Ch
ESI DAC1 7	ESIDAC1R7	04Eh
ESI DAC2 0	ESIDAC2R0	050h
ESI DAC2 1	ESIDAC2R1	052h
ESI DAC2 2	ESIDAC2R2	054h
ESI DAC2 3	ESIDAC2R3	056h
ESI DAC2 4	ESIDAC2R4	058h
ESI DAC2 5	ESIDAC2R5	05Ah
ESI DAC2 6	ESIDAC2R6	05Ch
ESI DAC2 7	ESIDAC2R7	05Eh
ESI TSM 0	ESITSM0	060h
ESI TSM 1	ESITSM1	062h
ESI TSM 2	ESITSM2	064h
ESI TSM 3	ESITSM3	066h
ESI TSM 4	ESITSM4	068h
ESI TSM 5	ESITSM5	06Ah
ESI TSM 6	ESITSM6	06Ch
ESI TSM 7	ESITSM7	06Eh
ESI TSM 8	ESITSM8	070h
ESI TSM 9	ESITSM9	072h
ESI TSM 10	ESITSM10	074h
ESI TSM 11	ESITSM11	076h
ESI TSM 12	ESITSM12	078h
ESI TSM 13	ESITSM13	07Ah
ESI TSM 14	ESITSM14	07Ch
ESI TSM 15	ESITSM15	07Eh
ESI TSM 16	ESITSM16	080h
ESI TSM 17	ESITSM17	082h
ESI TSM 18	ESITSM18	084h
ESI TSM 19	ESITSM19	086h
ESI TSM 20	ESITSM20	088h
ESI TSM 21	ESITSM21	08Ah
ESI TSM 22	ESITSM22	08Ch
ESI TSM 23	ESITSM23	08Eh
ESI TSM 24	ESITSM24	090h
ESI TSM 25	ESITSM25	092h
ESI TSM 26	ESITSM26	094h
ESI TSM 27	ESITSM27	096h
ESI TSM 28	ESITSM28	098h
ESI TSM 29	ESITSM29	09Ah
ESI TSM 30	ESITSM30	09Ch
ESI TSM 31	ESITSM31	09Eh

5.14 Identification

5.14.1 Revision Identification

The device revision information is shown as part of the top-side marking on the device package. The device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices in this data sheet, see Section 7.3.

The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For details on this value, see the "Hardware Revision" entries in Section 5.12.

5.14.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices in this data sheet, see Section 7.3.

A device identification value is also stored in the Device Descriptor structure in the Info Block section. For details on this value, see the "Device ID" entries in Section 5.12.

5.14.3 JTAG Identification

Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in detail in MSP430 Programming With the JTAG Interface.

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5 Detailed Description

5.1 Overview

5.2 CPU

5.3 Operating Modes

Table 5-1 Operating Modes

5.3.1 Peripherals in Low-Power Modes

Table 5-2 Peripheral States

5.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4

Table 5-3 Peripheral Groups

5.4 Interrupt Vector Table and Signatures

Table 5-4 Interrupt Sources, Flags, and Vectors

Table 5-5 Signatures

5.5 Bootloader (BSL)

Table 5-6 BSL Pin Requirements and Functions

5.6 JTAG Operation

5.6.1 JTAG Standard Interface

Table 5-7 JTAG Pin Requirements and Functions

5.6.2 Spy-Bi-Wire Interface

Table 5-8 Spy-Bi-Wire Pin Requirements and Functions

5.7 FRAM

5.8 RAM

5.9 Tiny RAM

5.10 Memory Protection Unit Including IP Encapsulation

5.11 Peripherals

5.11.1 Digital I/O

5.11.2 Oscillator and Clock System (CS)

5.11.3 Power-Management Module (PMM)

5.11.4 Hardware Multiplier (MPY)

5.11.5 Real-Time Clock (RTC_C)

5.11.6 Watchdog Timer (WDT_A)

Table 5-9 WDT_A Clocks

5.11.7 System Module (SYS)

Table 5-10 System Module Interrupt Vector Registers

5.11.8 DMA Controller

Table 5-11 DMA Trigger Assignments(1)

5.11.9 Enhanced Universal Serial Communication Interface (eUSCI)

5.11.10 Extended Scan Interface (ESI)

5.11.11 Timer_A TA0, Timer_A TA1

Table 5-12 Timer_A TA0 Signal Connections

Table 5-13 Timer_A TA1 Signal Connections

5.11.12 Timer_A TA2

Table 5-14 Timer_A TA2 Signal Connections

5.11.13 Timer_A TA3

Table 5-15 Timer_A TA3 Signal Connections

5.11.14 Timer_B TB0

Table 5-16 Timer_B TB0 Signal Connections

5.11.15 ADC12_B

Table 5-17 ADC12_B Trigger Signal Connections

Table 5-18 ADC12_B External and Internal Signal Mapping

5.11.16 Comparator_E

5.11.17 CRC16

5.11.18 CRC32

5.11.19 AES256 Accelerator

5.11.20 True Random Seed

5.11.21 Shared Reference (REF_A)

5.11.22 LCD_C

Table 5-19 LCD Automatic Charge Pump Disable Bits (LCDCPDISx)

5.11.23 Embedded Emulation

5.11.23.1 Embedded Emulation Module (EEM)

5.11.23.2 EnergyTrace++™ Technology

5.11.24 Input/Output Diagrams

5.11.24.1 Digital I/O Functionality – Ports P1 to P10

5.11.24.2 Capacitive Touch Functionality Ports P1 to P10 and PJ

5.11.24.3 Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger

Port P1 (P1.0 to P1.3) Pin Functions

5.11.24.4 Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger

Port P1 (P1.4 to P1.7) Pin Functions

5.11.24.5 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger

Port P2 (P2.0 to P2.3) Pin Functions

5.11.24.6 Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger

Port P2 (P2.4 to P2.7) Pin Functions

5.11.24.7 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger

Port P3 (P3.0 to P3.3) Pin Functions

Port P3 (P3.4 to P3.7) Pin Functions

5.11.24.8 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger

Port P4 (P4.0 to P4.3) Pin Functions

Table 5-11 DMA Trigger Assignments⁽¹⁾

Table 5-21 Device Descriptor Table ⁽¹⁾

Table 5-22 Memory Organization⁽¹⁾

Table 5-48 DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)