SLAS734 Data sheet

SLAS734G April 2011 – April 2016 MSP430G2203 , MSP430G2233 , MSP430G2303 , MSP430G2333 , MSP430G2403 , MSP430G2433 , MSP430G2533

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

PW|20
- MPDS362A
N|20
- MPDI002C
PW|28
- MPDS364
RHB|32
- MPQF130D

Thermal pad, mechanical data (Package|Pins)

RHB|32
- QFND029X

Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Voltage applied at V_CC to V_SS		–0.3	4.1	V
Voltage applied to any pin⁽²⁾		–0.3	V_CC + 0.3	V
Diode current at any device pin			±2	mA
Storage temperature, T_stg⁽³⁾	Unprogrammed device	–55	150	°C
Storage temperature, T_stg⁽³⁾	Programmed device	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. The JTAG fuse-blow voltage, V_FB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at V_CC = 3.3 V and T_A = 25°C (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage	During program execution	1.8		3.6	V
V_CC	Supply voltage	During flash programming or erase	2.2		3.6	V
V_SS	Supply voltage			0		V
T_A	Operating free-air temperature		–40		85	°C
f_SYSTEM	Processor frequency (maximum MCLK frequency using the USART module)⁽¹⁾⁽²⁾	V_CC = 1.8 V, Duty cycle = 50% ±10%	DC		6	MHz
		V_CC = 2.7 V, Duty cycle = 50% ±10%	DC		12
		V_CC = 3.3 V, Duty cycle = 50% ±10%	DC		16

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the specified maximum frequency.

(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 safe_op_area_las694.gif

NOTE:

Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V_CC of 2.2 V.

Figure 5-1 Safe Operating Area

5.4 Active Mode Supply Current Into V_CC Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
I_AM,1MHz	Active mode (AM) current at 1 MHz	f_DCO = f_MCLK = f_SMCLK = 1 MHz, f_ACLK = 0 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0	2.2 V		230		µA
I_AM,1MHz	Active mode (AM) current at 1 MHz		3 V		330	420	µA

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.

5.5 Typical Characteristics, Active Mode Supply Current (Into V_CC)

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_iam_vcc_las694.gif

Figure 5-2 Active Mode Current vs V_CC, T_A = 25°C

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_iam_fdco_las694.gif

Figure 5-3 Active Mode Current vs DCO Frequency

5.6 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾ ⁽²⁾

PARAMETER		TEST CONDITIONS	T_A	V_CC	TYP	MAX	UNIT
I_LPM0,1MHz	Low-power mode 0 (LPM0) current⁽³⁾	f_MCLK = 0 MHz, f_SMCLK = f_DCO = 1 MHz, f_ACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0	25°C	2.2 V	56		µA
I_LPM2	Low-power mode 2 (LPM2) current⁽⁴⁾	f_MCLK = f_SMCLK = 0 MHz, f_DCO = 1 MHz, f_ACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0	25°C	2.2 V	22		µA
I_LPM3,LFXT1	Low-power mode 3 (LPM3) current⁽⁴⁾	f_DCO = f_MCLK = f_SMCLK = 0 MHz, f_ACLK = 32768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0	25°C	2.2 V	0.7	1.5	µA
I_LPM3,VLO	Low-power mode 3 current, (LPM3)⁽⁴⁾	f_DCO = f_MCLK = f_SMCLK = 0 MHz, f_ACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0	25°C	2.2 V	0.5	0.7	µA
I_LPM4	Low-power mode 4 (LPM4) current⁽⁵⁾	f_DCO = f_MCLK = f_SMCLK = 0 MHz, f_ACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1	25°C	2.2 V	0.1	0.5	µA
I_LPM4	Low-power mode 4 (LPM4) current⁽⁵⁾		85°C	2.2 V	0.8	1.7	µA

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF.

(3) Current for brownout and WDT clocked by SMCLK included.

(4) Current for brownout and WDT clocked by ACLK included.

(5) Current for brownout included.

5.7 Typical Characteristics, Low-Power Mode Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_ilpm3_ta_las694.gif

Figure 5-4 LPM3 Current vs Temperature

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_ilpm4_ta_las694.gif

Figure 5-5 LPM4 Current vs Temperature

5.8 Thermal Resistance Characteristics

PARAMETER			VALUE ⁽⁴⁾	UNIT
Rθ_JA	Junction-to-ambient thermal resistance, still air ⁽¹⁾	VQFN (RHB-32)	32.1	°C/W
		TSSOP (PW-28)	72.2
		TSSOP (PW-20)	86.5
		PDIP (N-20)	49.3
Rθ_JC(TOP)	Junction-to-case (top) thermal resistance ⁽²⁾	VQFN (RHB-32)	22.3	°C/W
		TSSOP (PW-28)	18.3
		TSSOP (PW-20)	20.8
		PDIP (N-20)	41
Rθ_JC(BOTTOM)	Junction-to-case (bottom) thermal resistance	VQFN (RHB-32)	1.4	°C/W
		TSSOP (PW-28)	N/A
		TSSOP (PW-20)	N/A
		PDIP (N-20)	N/A
θ_JB	Junction-to-board thermal resistance ⁽³⁾	VQFN (RHB-32)	6.1	°C/W
		TSSOP (PW-28)	30.4
		TSSOP (PW-20)	39
		PDIP (N-20)	30.2
Ψ_JT	Junction-to-package-top characterization parameter	VQFN (RHB-32)	0.3	°C/W
		TSSOP (PW-28)	0.7
		TSSOP (PW-20)	0.8
		PDIP (N-20)	18.1
Ψ_JB	Junction-to-board characterization parameter	VQFN (RHB-32)	6.1	°C/W
		TSSOP (PW-28)	29.9
		TSSOP (PW-20)	38.1
		PDIP (N-20)	30.1

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(4) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (Rθ_JC) value, which is based on a JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC standards:

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

5.9 Schmitt-Trigger Inputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_IT+	Positive-going input threshold voltage			0.45 V_CC		0.75 V_CC	V
V_IT+	Positive-going input threshold voltage		3 V	1.35		2.25	V
V_IT–	Negative-going input threshold voltage			0.25 V_CC		0.55 V_CC	V
V_IT–	Negative-going input threshold voltage		3 V	0.75		1.65	V
V_hys	Input voltage hysteresis (V_IT+ – V_IT–)		3 V	0.3		1	V
R_Pull	Pullup or pulldown resistor	For pullup: V_IN = V_SS For pulldown: V_IN = V_CC	3 V	20	35	50	kΩ
C_I	Input capacitance	V_IN = V_SS or V_CC			5		pF

5.10 Leakage Current, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
I_lkg(Px.y)	High-impedance leakage current	See ⁽¹⁾ ⁽²⁾	3 V		±50	nA

(1) The leakage current is measured with V_SS or V_CC applied to the corresponding pins, unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.

5.11 Outputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_(OHmax) = –6 mA⁽¹⁾	3 V		V_CC – 0.3		V
V_OL	Low-level output voltage	I_(OLmax) = 6 mA⁽¹⁾	3 V		V_SS + 0.3		V

(1) The maximum total current, I_(OHmax) and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.

5.12 Output Frequency, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_Px.y	Port output frequency (with load)	Px.y, C_L = 20 pF, R_L = 1 kΩ⁽¹⁾ ⁽²⁾	3 V		12		MHz
f_{Port_CLK}	Clock output frequency	Px.y, C_L = 20 pF⁽²⁾	3 V		16		MHz

(1) A resistive divider with two 50-kΩ resistors between V_CC and V_SS is used as load. The output is connected to the center tap of the divider.

(2) The output voltage reaches at least 10% and 90% V_CC at the specified toggle frequency.

5.13 Typical Characteristics – Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_iol_vol_2p2v_las694.gif

Figure 5-6 Typical Low-Level Output Current vs Low-Level Output Voltage

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_ioh_voh_2p2v_las694.gif

Figure 5-8 Typical High-Level Output Current vs High-Level Output Voltage

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_iol_vol_3v_las694.gif

Figure 5-7 Typical Low-Level Output Current vs Low-Level Output Voltage

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_ioh_voh_3v_las694.gif

Figure 5-9 Typical High-Level Output Current vs High-Level Output Voltage

5.14 Pin-Oscillator Frequency – Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	TYP	UNIT
fo_P1.x	Port output oscillation frequency	P1.y, C_L = 10 pF, R_L = 100 kΩ⁽¹⁾⁽²⁾	3 V	1400	kHz
fo_P1.x	Port output oscillation frequency	P1.y, C_L = 20 pF, R_L = 100 kΩ⁽¹⁾⁽²⁾	3 V	900	kHz
fo_P2.x	Port output oscillation frequency	P2.0 to P2.5, C_L = 10 pF, R_L = 100 kΩ⁽¹⁾⁽²⁾	3 V	1800	kHz
fo_P2.x	Port output oscillation frequency	P2.0 to P2.5, C_L = 20 pF, R_L = 100 kΩ⁽¹⁾⁽²⁾	3 V	1000	kHz
fo_P2.6/7	Port output oscillation frequency	P2.6 and P2.7, C_L = 20 pF, R_L = 100 kΩ⁽¹⁾⁽²⁾	3 V	700	kHz
fo_P3.x	Port output oscillation frequency	P3.y, C_L = 10 pF, R_L = 100 kΩ⁽¹⁾⁽²⁾	3 V	1800	kHz
fo_P3.x	Port output oscillation frequency	P3.y, C_L = 20 pF, R_L = 100 kΩ⁽¹⁾⁽²⁾	3 V	1000	kHz

(1) A resistive divider with two 50-kΩ resistors between V_CC and V_SS is used as load. The output is connected to the center tap of the divider.

(2) The output voltage reaches at least 10% and 90% V_CC at the specified toggle frequency.

5.15 Typical Characteristics – Pin-Oscillator Frequency

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_fosc_cload_vcc3_las734.gif

NOTE:

One output active at a time.

Figure 5-10 Typical Oscillating Frequency vs Load Capacitance

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_fosc_cload_vcc2p2_las734.gif

NOTE:

One output active at a time.

Figure 5-11 Typical Oscillating Frequency vs Load Capacitance

5.16 POR, BOR⁽¹⁾⁽²⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	UNIT
V_CC(start)	See Figure 5-12	dV_CC/dt ≤ 3 V/s			0.7 V_{(B_IT--)}	V
V_{(B_IT–)}	See Figure 5-12 through Figure 5-14	dV_CC/dt ≤ 3 V/s			1.35	V
V_{hys(B_IT–)}	See Figure 5-12	dV_CC/dt ≤ 3 V/s			140	mV
t_d(BOR)	See Figure 5-12				2000	µs
t_(reset)	Pulse duration needed at RST/NMI pin to accepted reset internally		2.2 V	2		µs

(1) The current consumption of the brownout module is already included in the I_CC current consumption data. The voltage level V_{(B_IT–)} + V_{hys(B_IT–)} is ≤ 1.8 V.

(2) During power up, the CPU begins code execution following a period of t_d(BOR) after V_CC = V_{(B_IT–)} + V_{hys(B_IT–)}. The default DCO settings must not be changed until V_CC ≥ V_CC(min), where V_CC(min) is the minimum supply voltage for the desired operating frequency.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 por_bor_vcc_las694.gif

Figure 5-12 POR and BOR vs Supply Voltage

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 vccdrop_square_las694.gif

Figure 5-13 V_CC(drop) Level With a Square Voltage Drop to Generate a POR or BOR Signal

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 vccdrop_triangle_las694.gif

Figure 5-14 V_CC(drop) Level With a Triangle Voltage Drop to Generate a POR or BOR Signal

5.17 Main DCO Characteristics

All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter S_DCO.
Modulation control bits MODx select how often f_{DCO(RSEL,DCO+1)} is used within the period of 32 DCOCLK cycles. The frequency f_{DCO(RSEL,DCO)} is used for the remaining cycles. The frequency is an average equal to:

5.18 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_CC	Supply voltage	RSELx < 14		1.8		3.6	V
		RSELx = 14		2.2		3.6
		RSELx = 15		3		3.6
f_DCO(0,0)	DCO frequency (0, 0)	RSELx = 0, DCOx = 0, MODx = 0	3 V	0.06		0.14	MHz
f_DCO(0,3)	DCO frequency (0, 3)	RSELx = 0, DCOx = 3, MODx = 0	3 V	0.07		0.17	MHz
f_DCO(1,3)	DCO frequency (1, 3)	RSELx = 1, DCOx = 3, MODx = 0	3 V		0.15		MHz
f_DCO(2,3)	DCO frequency (2, 3)	RSELx = 2, DCOx = 3, MODx = 0	3 V		0.21		MHz
f_DCO(3,3)	DCO frequency (3, 3)	RSELx = 3, DCOx = 3, MODx = 0	3 V		0.30		MHz
f_DCO(4,3)	DCO frequency (4, 3)	RSELx = 4, DCOx = 3, MODx = 0	3 V		0.41		MHz
f_DCO(5,3)	DCO frequency (5, 3)	RSELx = 5, DCOx = 3, MODx = 0	3 V		0.58		MHz
f_DCO(6,3)	DCO frequency (6, 3)	RSELx = 6, DCOx = 3, MODx = 0	3 V	0.54		1.06	MHz
f_DCO(7,3)	DCO frequency (7, 3)	RSELx = 7, DCOx = 3, MODx = 0	3 V	0.80		1.50	MHz
f_DCO(8,3)	DCO frequency (8, 3)	RSELx = 8, DCOx = 3, MODx = 0	3 V		1.6		MHz
f_DCO(9,3)	DCO frequency (9, 3)	RSELx = 9, DCOx = 3, MODx = 0	3 V		2.3		MHz
f_DCO(10,3)	DCO frequency (10, 3)	RSELx = 10, DCOx = 3, MODx = 0	3 V		3.4		MHz
f_DCO(11,3)	DCO frequency (11, 3)	RSELx = 11, DCOx = 3, MODx = 0	3 V		4.25		MHz
f_DCO(12,3)	DCO frequency (12, 3)	RSELx = 12, DCOx = 3, MODx = 0	3 V	4.30		7.30	MHz
f_DCO(13,3)	DCO frequency (13, 3)	RSELx = 13, DCOx = 3, MODx = 0	3 V	6.00		9.60	MHz
f_DCO(14,3)	DCO frequency (14, 3)	RSELx = 14, DCOx = 3, MODx = 0	3 V	8.60		13.9	MHz
f_DCO(15,3)	DCO frequency (15, 3)	RSELx = 15, DCOx = 3, MODx = 0	3 V	12.0		18.5	MHz
f_DCO(15,7)	DCO frequency (15, 7)	RSELx = 15, DCOx = 7, MODx = 0	3 V	16.0		26.0	MHz
S_RSEL	Frequency step between range RSEL and RSEL+1	S_RSEL = f_{DCO(RSEL+1,DCO)}/f_{DCO(RSEL,DCO)}	3 V		1.35		ratio
S_DCO	Frequency step between tap DCO and DCO+1	S_DCO = f_{DCO(RSEL,DCO+1)}/f_{DCO(RSEL,DCO)}	3 V		1.08		ratio
Duty cycle		Measured at SMCLK output	3 V		50%

5.19 Calibrated DCO Frequencies, Tolerance

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER	TEST CONDITIONS	T_A	V_CC	MIN	TYP	MAX
1-MHz tolerance over temperature⁽¹⁾	BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V	0°C to 85°C	3 V	–3%	±0.5%	+3%
1-MHz tolerance over V_CC	BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V	30°C	1.8 V to 3.6 V	–3%	±2%	+3%
1-MHz tolerance overall	BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V	–40°C to 85°C	1.8 V to 3.6 V	–6%	±3%	+6%
8-MHz tolerance over temperature⁽¹⁾	BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3 V	0°C to 85°C	3 V	–3%	±0.5%	+3%
8-MHz tolerance over V_CC	BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3 V	30°C	2.2 V to 3.6 V	–3%	±2%	+3%
8-MHz tolerance overall	BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3 V	–40°C to 85°C	2.2 V to 3.6 V	–6%	±3%	+6%
12-MHz tolerance over temperature⁽¹⁾	BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30°C and 3 V	0°C to 85°C	3 V	–3%	±0.5%	+3%
12-MHz tolerance over V_CC	BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30°C and 3 V	30°C	2.7 V to 3.6 V	–3%	±2%	+3%
12-MHz tolerance overall	BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30°C and 3 V	–40°C to 85°C	2.7 V to 3.6 V	–6%	±3%	+6%
16-MHz tolerance over temperature⁽¹⁾	BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30°C and 3 V	0°C to 85°C	3 V	–3%	±0.5%	+3%
16-MHz tolerance over V_CC	BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30°C and 3 V	30°C	3.3 V to 3.6 V	–3%	±2%	+3%
16-MHz tolerance overall	BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30°C and 3 V	–40°C to 85°C	3.3 V to 3.6 V	–6%	±3%	+6%

(1) This is the frequency change from the measured frequency at 30°C over temperature.

5.20 Wake-up Times From Lower-Power Modes (LPM3, LPM4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
t_DCO,LPM3/4	DCO clock wake-up time from LPM3 or LPM4⁽¹⁾	BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz	3 V		1.5		µs
t_CPU,LPM3/4	CPU wake-up time from LPM3 or LPM4⁽²⁾			1/f_MCLK + t_Clock,LPM3/4

(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK).

(2) Parameter applicable only if DCOCLK is used for MCLK.

5.21 Typical Characteristics, DCO Clock Wake-up Time From LPM3 or LPM4

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 g_tdcowake_fdco_las694.gif

Figure 5-15 DCO Wake-up Time From LPM3 vs DCO Frequency

5.22 Crystal Oscillator, XT1, Low-Frequency Mode⁽⁴⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_LFXT1,LF	LFXT1 oscillator crystal frequency, LF mode 0, 1	XTS = 0, LFXT1Sx = 0 or 1	1.8 V to 3.6 V		32768		Hz
f_{LFXT1,LF,logic}	LFXT1 oscillator logic level square-wave input frequency, LF mode	XTS = 0, XCAPx = 0, LFXT1Sx = 3	1.8 V to 3.6 V	10000	32768	50000	Hz
OA_LF	Oscillation allowance for LF crystals	XTS = 0, LFXT1Sx = 0, f_LFXT1,LF = 32768 Hz, C_L,eff = 6 pF			500		kΩ
OA_LF	Oscillation allowance for LF crystals	XTS = 0, LFXT1Sx = 0, f_LFXT1,LF = 32768 Hz, C_L,eff = 12 pF			200		kΩ
C_L,eff	Integrated effective load capacitance, LF mode⁽¹⁾	XTS = 0, XCAPx = 0			1		pF
		XTS = 0, XCAPx = 1			5.5
		XTS = 0, XCAPx = 2			8.5
		XTS = 0, XCAPx = 3			11
	Duty cycle, LF mode	XTS = 0, Measured at P2.0/ACLK, f_LFXT1,LF = 32768 Hz	2.2 V	30%	50%	70%
f_Fault,LF	Oscillator fault frequency, LF mode⁽³⁾	XTS = 0, XCAPx = 0, LFXT1Sx = 3⁽²⁾	2.2 V	10		10000	Hz

(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.

(2) Measured with logic-level input frequency but also applies to operation with crystals.

(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag.

(4) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.

5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		T_A	V_CC	MIN	TYP	MAX	UNIT
f_VLO	VLO frequency	–40°C to 85°C	3 V	4	12	20	kHz
df_VLO/d_T	VLO frequency temperature drift	–40°C to 85°C	3 V		0.5		%/°C
df_VLO/dV_CC	VLO frequency supply voltage drift	25°C	1.8 V to 3.6 V		4		%/V

5.24 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_TA	Timer_A input clock frequency	SMCLK, duty cycle = 50% ±10%			f_SYSTEM		MHz
t_TA,cap	Timer_A capture timing	TA0, TA1	3 V	20			ns

5.25 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_USCI	USCI input clock frequency	SMCLK, duty cycle = 50% ±10%			f_SYSTEM		MHz
f_max,BITCLK	Maximum BITCLK clock frequency (equals baud rate in MBaud)⁽¹⁾		3 V	2			MHz
t_τ	UART receive deglitch time⁽²⁾		3 V	50	100	600	ns

(1) The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz.

(2) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time.

5.26 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16 and Figure 5-17)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
f_USCI	USCI input clock frequency	SMCLK, duty cycle = 50% ±10%			f_SYSTEM	MHz
t_SU,MI	SOMI input data setup time		3 V	75		ns
t_HD,MI	SOMI input data hold time		3 V	0		ns
t_VALID,MO	SIMO output data valid time	UCLK edge to SIMO valid, C_L = 20 pF	3 V		20	ns

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 t_usci_spi_master_ckph0_las734.gif

Figure 5-16 SPI Master Mode, CKPH = 0

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 t_usci_spi_master_ckph1_las734.gif

Figure 5-17 SPI Master Mode, CKPH = 1

5.27 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18 and Figure 5-19)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
t_STE,LEAD	STE lead time, STE low to clock		3 V		50		ns
t_STE,LAG	STE lag time, Last clock to STE high		3 V	10			ns
t_STE,ACC	STE access time, STE low to SOMI data out		3 V		50		ns
t_STE,DIS	STE disable time, STE high to SOMI high impedance		3 V		50		ns
t_SU,SI	SIMO input data setup time		3 V	15			ns
t_HD,SI	SIMO input data hold time		3 V	10			ns
t_VALID,SO	SOMI output data valid time	UCLK edge to SOMI valid, C_L = 20 pF	3 V		50	75	ns

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 t_usci_spi_slave_ckph0_las734.gif

Figure 5-18 SPI Slave Mode, CKPH = 0

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 t_usci_spi_slave_ckph1_las734.gif

Figure 5-19 SPI Slave Mode, CKPH = 1

5.28 USCI (I²C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-20)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_USCI	USCI input clock frequency	SMCLK, duty cycle = 50% ±10%				f_SYSTEM	MHz
f_SCL	SCL clock frequency		3 V	0		400	kHz
t_HD,STA	Hold time (repeated) START	f_SCL ≤ 100 kHz	3 V	4.0			µs
t_HD,STA	Hold time (repeated) START	f_SCL > 100 kHz	3 V	0.6			µs
t_SU,STA	Setup time for a repeated START	f_SCL ≤ 100 kHz	3 V	4.7			µs
t_SU,STA	Setup time for a repeated START	f_SCL > 100 kHz	3 V	0.6			µs
t_HD,DAT	Data hold time		3 V	0			ns
t_SU,DAT	Data setup time		3 V	250			ns
t_SU,STO	Setup time for STOP		3 V	4.0			µs
t_SP	Pulse duration of spikes suppressed by input filter		3 V	50	100	600	ns

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 t_usci_i2c_las734.gif

Figure 5-20 I²C Mode Timing

5.29 10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	T_A	V_CC	MIN	TYP	MAX	UNIT
V_CC	Analog supply voltage	V_SS = 0 V			2.2		3.6	V
V_Ax	Analog input voltage⁽²⁾	All Ax terminals, Analog inputs selected in ADC10AE register		3 V	0		V_CC	V
I_ADC10	ADC10 supply current⁽³⁾	f_ADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 0, ADC10SHT0 = 1, ADC10SHT1 = 0, ADC10DIV = 0	25°C	3 V		0.6		mA
I_REF+	Reference supply current, reference buffer disabled⁽⁴⁾	f_ADC10CLK = 5.0 MHz, ADC10ON = 0, REF2_5V = 0, REFON = 1, REFOUT = 0	25°C	3 V		0.25		mA
I_REF+	Reference supply current, reference buffer disabled⁽⁴⁾	f_ADC10CLK = 5.0 MHz, ADC10ON = 0, REF2_5V = 1, REFON = 1, REFOUT = 0	25°C	3 V		0.25		mA
I_REFB,0	Reference buffer supply current with ADC10SR = 0⁽⁴⁾	f_ADC10CLK = 5.0 MHz, ADC10ON = 0, REFON = 1, REF2_5V = 0, REFOUT = 1, ADC10SR = 0	25°C	3 V		1.1		mA
I_REFB,1	Reference buffer supply current with ADC10SR = 1⁽⁴⁾	f_ADC10CLK = 5.0 MHz, ADC10ON = 0, REFON = 1, REF2_5V = 0, REFOUT = 1, ADC10SR = 1	25°C	3 V		0.5		mA
C_I	Input capacitance	Only one terminal Ax can be selected at one time	25°C	3 V			27	pF
R_I	Input MUX ON resistance	0 V ≤ V_Ax ≤ V_CC	25°C	3 V		1000		Ω

(1) The leakage current is defined in the leakage current table with Px.y/Ax parameter.

(2) The analog input voltage range must be within the selected reference voltage range V_R+ to V_R– for valid conversion results.

(3) The internal reference supply current is not included in current consumption parameter I_ADC10.

(4) The internal reference current is supplied through terminal V_CC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

5.30 10-Bit ADC, Built-In Voltage Reference (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_CC,REF+	Positive built-in reference analog supply voltage range	I_VREF+ ≤ 1 mA, REF2_5V = 0		2.2			V
V_CC,REF+	Positive built-in reference analog supply voltage range	I_VREF+ ≤ 1 mA, REF2_5V = 1		2.9			V
V_REF+	Positive built-in reference voltage	I_VREF+ ≤ I_VREF+max, REF2_5V = 0	3 V	1.41	1.5	1.59	V
V_REF+	Positive built-in reference voltage	I_VREF+ ≤ I_VREF+max, REF2_5V = 1	3 V	2.35	2.5	2.65	V
I_LD,VREF+	Maximum VREF+ load current		3 V			±1	mA
	VREF+ load regulation	I_VREF+ = 500 µA ±100 µA, Analog input voltage V_Ax ≈ 0.75 V, REF2_5V = 0	3 V			±2	LSB
	VREF+ load regulation	I_VREF+ = 500 µA ±100 µA, Analog input voltage V_Ax ≈ 1.25 V, REF2_5V = 1	3 V			±2	LSB
	V_REF+ load regulation response time	I_VREF+ = 100 µA → 900 µA, V_Ax ≈ 0.5 × VREF+, Error of conversion result ≤ 1 LSB, ADC10SR = 0	3 V			400	ns
C_VREF+	Maximum capacitance at pin VREF+	I_VREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1	3 V			100	pF
TC_REF+	Temperature coefficient	I_VREF+ = const with 0 mA ≤ I_VREF+ ≤ 1 mA	3 V			±100	ppm/ °C
t_REFON	Settling time of internal reference voltage to 99.9% VREF	I_VREF+ = 0.5 mA, REF2_5V = 0, REFON = 0 → 1	3.6 V			30	µs
t_REFBURST	Settling time of reference buffer to 99.9% VREF	I_VREF+ = 0.5 mA, REF2_5V = 1, REFON = 1, REFBURST = 1, ADC10SR = 0	3 V			2	µs

5.31 10-Bit ADC, External Reference⁽¹⁾ (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
VEREF+	Positive external reference input voltage range ⁽²⁾	VEREF+ > VEREF–, SREF1 = 1, SREF0 = 0		1.4		V_CC	V
VEREF+	Positive external reference input voltage range ⁽²⁾	VEREF– ≤ VEREF+ ≤ V_CC – 0.15 V, SREF1 = 1, SREF0 = 1 ⁽³⁾		1.4		3	V
VEREF–	Negative external reference input voltage range ⁽⁴⁾	VEREF+ > VEREF–		0		1.2	V
ΔVEREF	Differential external reference input voltage range, ΔVEREF = VEREF+ – VEREF–	VEREF+ > VEREF– ⁽⁵⁾		1.4		V_CC	V
I_VEREF+	Static input current into VEREF+	0 V ≤ VEREF+ ≤ V_CC, SREF1 = 1, SREF0 = 0	3 V		±1		µA
I_VEREF+	Static input current into VEREF+	0 V ≤ VEREF+ ≤ V_CC – 0.15 V ≤ 3 V, SREF1 = 1, SREF0 = 1⁽³⁾	3 V		0		µA
I_VEREF–	Static input current into VEREF–	0 V ≤ VEREF– ≤ V_CC	3 V		±1		µA

(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C_I, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements.

(3) Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply current I_REFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.

(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements.

(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.

5.32 10-Bit ADC, Timing Parameters (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS		V_CC	MIN	TYP	MAX	UNIT
f_ADC10CLK	ADC10 input clock frequency	For specified performance of ADC10 linearity parameters	ADC10SR = 0	3 V	0.45		6.3	MHz
f_ADC10CLK	ADC10 input clock frequency	For specified performance of ADC10 linearity parameters	ADC10SR = 1	3 V	0.45		1.5	MHz
f_ADC10OSC	ADC10 built-in oscillator frequency	ADC10DIVx = 0, ADC10SSELx = 0, f_ADC10CLK = f_ADC10OSC		3 V	3.7		6.3	MHz
t_CONVERT	Conversion time	ADC10 built-in oscillator, ADC10SSELx = 0, f_ADC10CLK = f_ADC10OSC		3 V	2.06		3.51	µs
t_CONVERT	Conversion time	f_ADC10CLK from ACLK, MCLK, or SMCLK: ADC10SSELx ≠ 0				13 × ADC10DIV × 1 / f_ADC10CLK		µs
t_ADC10ON	Turnon settling time of the ADC	⁽¹⁾					100	ns

(1) The condition is that the error in a conversion started after t_ADC10ON is less than ±0.5 LSB. The reference and input signal are already settled.

5.33 10-Bit ADC, Linearity Parameters (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	TYP	MAX	UNIT
E_I	Integral linearity error		3 V		±1	LSB
E_D	Differential linearity error		3 V		±1	LSB
E_O	Offset error	Source impedance R_S < 100 Ω	3 V		±1	LSB
E_G	Gain error		3 V	±1.1	±2	LSB
E_T	Total unadjusted error		3 V	±2	±5	LSB

5.34 10-Bit ADC, Temperature Sensor and Built-In V_MID (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
I_SENSOR	Temperature sensor supply current⁽¹⁾	REFON = 0, INCHx = 0Ah, T_A = 25°C	3 V		60		µA
TC_SENSOR		ADC10ON = 1, INCHx = 0Ah ⁽²⁾	3 V		3.55		mV/°C
t_{Sensor(sample)}	Sample time required if channel 10 is selected ⁽³⁾	ADC10ON = 1, INCHx = 0Ah, Error of conversion result ≤ 1 LSB	3 V	30			µs
I_VMID	Current into divider at channel 11	ADC10ON = 1, INCHx = 0Bh	3 V			⁽⁴⁾	µA
V_MID	V_CC divider at channel 11	ADC10ON = 1, INCHx = 0Bh, V_MID ≈ 0.5 × V_CC	3 V		1.5		V
t_VMID(sample)	Sample time required if channel 11 is selected ⁽⁵⁾	ADC10ON = 1, INCHx = 0Bh, Error of conversion result ≤ 1 LSB	3 V	1220			ns

(1) The sensor current I_SENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is high). When REFON = 1, I_SENSOR is included in I_REF+. When REFON = 0, I_SENSOR applies during conversion of the temperature sensor input (INCH = 0Ah).

(2) The following formula can be used to calculate the temperature sensor output voltage:
V_Sensor,typ = TC_Sensor (273 + T [°C] ) + V_{Offset,sensor} [mV] or
V_Sensor,typ = TC_Sensor T [°C] + V_Sensor(T_A = 0°C) [mV]

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on).

(4) No additional current is needed. The V_MID is used during sampling.

(5) The on-time t_VMID(on) is included in the sampling time t_VMID(sample); no additional on time is needed.

5.35 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_{CC(PGM/ERASE)}	Program and erase supply voltage			2.2		3.6	V
f_FTG	Flash timing generator frequency			257		476	kHz
I_PGM	Supply current from V_CC during program		2.2 V, 3.6 V		1	5	mA
I_ERASE	Supply current from V_CC during erase		2.2 V, 3.6 V		1	7	mA
t_CPT	Cumulative program time⁽¹⁾		2.2 V, 3.6 V			10	ms
t_CMErase	Cumulative mass erase time		2.2 V, 3.6 V	20			ms
	Program and erase endurance			10⁴	10⁵		cycles
t_Retention	Data retention duration	T_J = 25°C		100			years
t_Word	Word or byte program time	See ⁽²⁾			30		t_FTG
t_{Block, 0}	Block program time for first byte or word	See ⁽²⁾			25		t_FTG
t_{Block, 1-63}	Block program time for each additional byte or word	See ⁽²⁾			18		t_FTG
t_{Block, End}	Block program end-sequence wait time	See ⁽²⁾			6		t_FTG
t_{Mass Erase}	Mass erase time	See ⁽²⁾			10593		t_FTG
t_{Seg Erase}	Segment erase time	See ⁽²⁾			4819		t_FTG

(1) Do not exceed the cumulative program time when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word or byte write and block write modes.

(2) These values are hardwired into the state machine of the flash controller (t_FTG = 1/f_FTG).

5.36 RAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_(RAMh)	RAM retention supply voltage ⁽¹⁾	CPU halted	1.6		V

(1) This parameter defines the minimum supply voltage V_CC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition.

5.37 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		V_CC	MIN	TYP	MAX	UNIT
f_SBW	Spy-Bi-Wire input frequency	2.2 V	0		20	MHz
t_SBW,Low	Spy-Bi-Wire low clock pulse duration	2.2 V	0.025		15	µs
t_SBW,En	Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge⁽¹⁾)	2.2 V			1	µs
t_SBW,Ret	Spy-Bi-Wire return to normal operation time	2.2 V	15		100	µs
f_TCK	TCK input frequency⁽²⁾	2.2 V	0		5	MHz
R_Internal	Internal pulldown resistance on TEST	2.2 V	25	60	90	kΩ

(1) Tools that access the Spy-Bi-Wire interface must wait for the maximum t_SBW,En time after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge.

(2) f_TCK may be restricted to meet the timing requirements of the module selected.

5.38 JTAG Fuse⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_CC(FB)	Supply voltage during fuse-blow condition	T_A = 25°C	2.5		V
V_FB	Voltage level on TEST for fuse blow		6	7	V
I_FB	Supply current into TEST during fuse blow			100	mA
t_FB	Time to blow fuse			1	ms

(1) After the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation features is possible, and JTAG is switched to bypass mode.

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings(1)

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Active Mode Supply Current Into VCC Excluding External Current

5.5 Typical Characteristics, Active Mode Supply Current (Into VCC)

5.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

5.7 Typical Characteristics, Low-Power Mode Supply Currents

5.8 Thermal Resistance Characteristics

5.9 Schmitt-Trigger Inputs, Ports Px

5.10 Leakage Current, Ports Px

5.11 Outputs, Ports Px

5.12 Output Frequency, Ports Px

5.13 Typical Characteristics – Outputs

5.14 Pin-Oscillator Frequency – Ports Px

5.15 Typical Characteristics – Pin-Oscillator Frequency

5.16 POR, BOR(1)(2)

5.17 Main DCO Characteristics

5.18 DCO Frequency

5.19 Calibrated DCO Frequencies, Tolerance

5.20 Wake-up Times From Lower-Power Modes (LPM3, LPM4)

5.21 Typical Characteristics, DCO Clock Wake-up Time From LPM3 or LPM4

5.22 Crystal Oscillator, XT1, Low-Frequency Mode(4)

5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

5.24 Timer_A

5.25 USCI (UART Mode)

5.26 USCI (SPI Master Mode)

5.27 USCI (SPI Slave Mode)

5.28 USCI (I2C Mode)

5.29 10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x33 Only)

5.30 10-Bit ADC, Built-In Voltage Reference (MSP430G2x33 Only)

5.31 10-Bit ADC, External Reference(1) (MSP430G2x33 Only)

5.32 10-Bit ADC, Timing Parameters (MSP430G2x33 Only)

5.33 10-Bit ADC, Linearity Parameters (MSP430G2x33 Only)

5.34 10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x33 Only)

5.35 Flash Memory

5.36 RAM

5.37 JTAG and Spy-Bi-Wire Interface

5.38 JTAG Fuse(1)

5.1 Absolute Maximum Ratings⁽¹⁾

5.4 Active Mode Supply Current Into V_CC Excluding External Current

5.5 Typical Characteristics, Active Mode Supply Current (Into V_CC)

5.6 Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

5.16 POR, BOR⁽¹⁾⁽²⁾

5.22 Crystal Oscillator, XT1, Low-Frequency Mode⁽⁴⁾

5.28 USCI (I²C Mode)

5.31 10-Bit ADC, External Reference⁽¹⁾ (MSP430G2x33 Only)

5.34 10-Bit ADC, Temperature Sensor and Built-In V_MID (MSP430G2x33 Only)

5.38 JTAG Fuse⁽¹⁾