SLAS887A September 2014 – May 2018
The MSP430i family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430i development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide.
|P1.0/UCA0STE/MCLK/TCK||IN||JTAG clock input|
|P1.1/UCA0CLK/SMCLK/TMS||IN||JTAG state control|
|P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK||IN||JTAG data input/TCLK input|
|P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI||OUT||JTAG data output|
|TEST/SBWTCK||IN||Enable JTAG pins|