SLAS887A September   2014  – May 2018

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current (Into VCC) Excluding External Current
    5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6 Thermal Resistance Characteristics
    7. 5.7 Timing and Switching Characteristics
      1. 5.7.1  Reset Timing
        1. Table 5-1 Reset Timing
      2. 5.7.2  Clock Specifications
        1. Table 5-2 DCO in External Resistor Mode
        2. Table 5-3 DCO in Internal Resistor Mode
        3. Table 5-4 DCO Overall Tolerance Table
        4. Table 5-5 DCO in Bypass Mode Recommended Operating Conditions
      3. 5.7.3  Wake-up Characteristics
        1. Table 5-6 Wake-up Times From Low Power Modes
      4. 5.7.4  I/O Ports
        1. Table 5-7   Schmitt-Trigger Inputs – General-Purpose I/O
        2. Table 5-8   Inputs – Ports P1 and P2
        3. Table 5-9   Leakage Current – General-Purpose I/O
        4. Table 5-10 Outputs – General-Purpose I/O
        5. Table 5-11 Output Frequency – General-Purpose I/O
        6. 5.7.4.1     Typical Characteristics – Outputs
      5. 5.7.5  Power Management Module
        1. Table 5-12 PMM, High-Side Brownout Reset (BORH)
        2. Table 5-13 PMM, Low-Side SVS (SVSL)
        3. Table 5-14 PMM, Core Voltage
        4. Table 5-15 PMM, Voltage Monitor (VMON)
      6. 5.7.6  Reference Module
        1. Table 5-16 Voltage Reference (REF)
        2. Table 5-17 Temperature Sensor
      7. 5.7.7  SD24
        1. Table 5-18 SD24 Power Supply and Recommended Operating Conditions
        2. Table 5-19 SD24 Internal Voltage Reference
        3. Table 5-20 SD24 External Voltage Reference
        4. Table 5-21 SD24 Input Range
        5. Table 5-22 SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256)
        6. Table 5-23 SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256)
      8. 5.7.8  eUSCI
        1. Table 5-24 eUSCI (UART Mode) Recommended Operating Conditions
        2. Table 5-25 eUSCI (UART Mode)
        3. Table 5-26 eUSCI (SPI Master Mode) Recommended Operating Conditions
        4. Table 5-27 eUSCI (SPI Master Mode)
        5. Table 5-28 eUSCI (SPI Slave Mode)
        6. Table 5-29 eUSCI (I2C Mode)
      9. 5.7.9  Timer_A
        1. Table 5-30 Timer_A
      10. 5.7.10 Flash
        1. Table 5-31 Flash Memory
      11. 5.7.11 Emulation and Debug
        1. Table 5-32 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagrams
    3. 6.3  CPU
    4. 6.4  Instruction Set
    5. 6.5  Operating Modes
    6. 6.6  Interrupt Vector Addresses
    7. 6.7  Special Function Registers
      1. Table 6-4 Interrupt Enable 1 (Address = 00h)
      2. Table 6-5 Interrupt Flag Register 1 (Address = 02h)
    8. 6.8  Flash Memory
    9. 6.9  JTAG Operation
      1. 6.9.1 JTAG Standard Interface
      2. 6.9.2 Spy-Bi-Wire Interface
      3. 6.9.3 JTAG Disable Register
        1. Table 6-1 SYSJTAGDIS Register
    10. 6.10 Peripherals
      1. 6.10.1 Clock System
      2. 6.10.2 Power-Management Module (PMM)
      3. 6.10.3 Digital I/O
      4. 6.10.4 Watchdog Timer (WDT)
      5. 6.10.5 Timer TA0
      6. 6.10.6 Timer TA1
      7. 6.10.7 Enhanced Universal Serial Communication Interface (eUSCI)
      8. 6.10.8 Hardware Multiplier
      9. 6.10.9 SD24
    11. 6.11 Input/Output Diagrams
      1. 6.11.1 Port P1, P1.0 to P1.3, Input/Output With Schmitt Trigger
      2. 6.11.2 Port P1, P1.4 to P1.7, Input/Output With Schmitt Trigger
      3. 6.11.3 Port P2, P2.0 to P2.2 and P2.4 to P2.7, Input/Output With Schmitt Trigger
      4. 6.11.4 Port P2, P2.3, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptor
    13. 6.13 Memory
      1. 6.13.1 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Device Identification
      2. 6.14.2 JTAG Identification
  7. 7Applications, Implementation, and Layout
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-22 SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SINAD Signal-to-noise + distortion ratio SD24GAINx = 1 fIN = 50 Hz(1) 3 V 84 89 dB
SD24GAINx = 2 89
SD24GAINx = 4 87
SD24GAINx = 8 83
SD24GAINx = 16 77
THD Total harmonic distortion SD24GAINx = 1 fIN = 50 Hz(1) 3 V 100 dB
SD24GAINx = 8 95
SD24GAINx = 16 90
SFDR Spurious-free dynamic range SD24GAINx = 1 fIN = 50 Hz(1) 3 V 100 dB
SD24GAINx = 8 95
SD24GAINx = 16 90
INL Integral nonlinearity, end-point fit SD24GAINx: 1, 8, 16 3 V –0.003 0.003 % FSR
G Nominal gain SD24GAINx = 1 3 V 1
SD24GAINx = 2 2
SD24GAINx = 4 4
SD24GAINx = 8 8
SD24GAINx = 16 16
EG Gain error SD24GAINx: 1, 8, 16 3 V –2% 2%
ΔEG/ ΔT Gain error temperature coefficient SD24GAINx: 1, 8, 16 3 V 50 ppm/°C
EOS Offset error SD24GAINx = 1 3 V 4 mV
SD24GAINx = 16 2
ΔEOS/ΔT Offset error temperature coefficient SD24GAINx = 1 3 V ±5 ±25 ppm FSR/°C
SD24GAINx = 16 ±3 ±10
CMRR,50Hz Common-mode rejection ratio at 50 Hz SD24GAINx = 1, Common-mode input signal:
VID = 928 mV, fIN = 50 Hz
3 V –55 dB
SD24GAINx = 16, Common-mode input signal:
VID = 58 mV, fIN = 50 Hz
–60
AC PSRR AC power supply rejection ratio SD24GAINx: 1, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC = 50 Hz,
Inputs grounded (no analog signal applied)
3 V –90 dB
SD24GAINx: 8, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC = 50 Hz,
Inputs grounded (no analog signal applied)
3 V –95
SD24GAINx: 16, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC = 50 Hz,
Inputs grounded (no analog signal applied)
3 V –95
XT Crosstalk between converters Crosstalk source: SD24GAINx = 1, Sine-wave with maximum possible VPP, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAINx = 1 3 V –120 dB
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum possible VPP, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAINx = 8 –110
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum possible VPP, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAINx = 16 –110
The following voltages are applied to the SD24 inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A–(t) = 0 V – VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) – VIN,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value allowed for a given range (according to SD24 input range).