SLAS887C September 2014 – March 2021
PRODUCTION DATA
The SYSJTAGDIS register can disable the JTAG port to provide code protection and device security. JTAG is disabled when software writes the value 0xA5A5 to this register within 64 MCLK clock cycles after a BOR or POR reset; otherwise, the JTAG port is enabled. Any writes to this register after the first 64 MCLK clock cycles are ignored. Reads from this register at any time return the JTAG enable or disable status. The value 0xA5A5 indicates that JTAG is disabled, and 0x9696 indicates that JTAG is enabled. The SYSJTAGDIS register is mapped to address 01FEh.
Application programming the device to any of the low power modes within first 64 MCLK clock cycles after a BOR or POR reset will lock the device for any JTAG/SBW access.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
JTAGKEY | |||||||
rw-[1] | rw-[0] | rw-[1] | rw-[0] | rw-[0] | rw-[1] | rw-[0] | rw-[1] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JTAGKEY | |||||||
rw-[1] | rw-[0] | rw-[1] | rw-[0] | rw-[0] | rw-[1] | rw-[0] | rw-[1] |
JTAGKEY | 0xA5A5 indicates JTAG is disabled and 0x9696 indicates JTAG is enabled. |