SLASF90C October   2023  – February 2025 MSPM0C1103 , MSPM0C1104

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 ADC
      1. 7.11.1 Electrical Characteristics
      2. 7.11.2 Switching Characteristics
      3. 7.11.3 Linearity Parameters
      4. 7.11.4 Typical Connection Diagram
    12. 7.12 Temperature Sensor
    13. 7.13 VREF
      1. 7.13.1 Voltage Characteristics
      2. 7.13.2 Electrical Characteristics
    14. 7.14 I2C
      1. 7.14.1 I2C Characteristics
      2. 7.14.2 I2C Filter
      3. 7.14.3 I2C Timing Diagram
    15. 7.15 SPI
      1. 7.15.1 SPI
      2. 7.15.2 SPI Timing Diagrams
    16. 7.16 UART
    17. 7.17 TIMx
    18. 7.18 Windowed Watchdog Characteristics
    19. 7.19 Emulation and Debug
      1. 7.19.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0C110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 CRC
    16. 8.16 UART
    17. 8.17 SPI
    18. 8.18 I2C
    19. 8.19 WWDT
    20. 8.20 Timers (TIMx)
    21. 8.21 Device Analog Connections
    22. 8.22 Input/Output Diagrams
    23. 8.23 Serial Wire Debug Interface
    24. 8.24 Device Factory Constants
    25. 8.25 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DYY|16
  • DDF|8
  • RUK|20
  • DGS|20
  • DSG|8
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Signal Descriptions

FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION
20 VSSOP 20 TSSOP 20 WQFN 16 SOT 8 SOT 8 WSON 8 DSBGA
ADC A0 2 2 20 - 1 1 B1 I ADC0 analog input 0
A1 1 1 19 1 - - - I ADC0 analog input 1
A2 20 20 18 16 - - - I ADC0 analog input 2
A3 19 19 17 15 8 8 A1 I ADC0 analog input 3
A4 17 17 15 13 - - - I ADC0 analog input 4
A5 3 3 1 2 - - - I ADC0 analog input 5
A6 16 16 14 12 7 7 C1 I ADC0 analog input 6
A7 14 14 12 10 - - - I ADC0 analog input 7
A8 12 - 10 - - - - I ADC0 analog input 8
A9 13 13 11 9 - - - I ADC0 analog input 9
Clock CLK_OUT 14, 17 14, 17 12, 15 10, 13 - - - O Configurable clock output
Debug SWDIO 15 15 13 11 6 6 D1 I/O Serial wire debug data input/output
SWCLK 16 16 14 12 7 7 C1 I Serial wire debug input clock
GPIO PA0 4 11 2 3 5 5 A2 I/O General-purpose digital I/O with open-drain capability
PA1 5 12 3 4 2 2 B2 I/O General-purpose digital I/O with open-drain capability
PA2 8 8 6 7 - - - I/O General-purpose digital I/O
PA4 9 5 7 - - - - I/O General-purpose digital I/O
PA6 10 10 8 8 - - - I/O General-purpose digital I/O
PA11 11 6 9 - - - - I/O General-purpose digital I/O
PA16 12 - 10 - - - - I/O General-purpose digital I/O
PA17 13 13 11 9 - - - I/O General-purpose digital I/O
PA18 14 14 12 10 - - - I/O General-purpose digital I/O
PA19 15 15 13 11 6 6 D1 I/O General-purpose digital I/O
PA20 16 16 14 12 7 7 C1 I/O General-purpose digital I/O
PA22 17 17 15 13 - - - I/O General-purpose digital I/O
PA23 18 18 16 14 - - - I/O General-purpose digital I/O
PA24 19 19 17 15 8 8 A1 I/O General-purpose digital I/O
PA25 20 20 18 16 - - - I/O General-purpose digital I/O
PA26 1 1 19 1 - - - I/O General-purpose digital I/O
PA27 2 2 20 - 1 1 B1 I/O General-purpose digital I/O
PA28 3 3 1 2 - - - I/O General-purpose digital I/O
I2C I2C0_SCL 5, 11 6 3, 9 4 2 2 B2 I/O I2C0 serial clock
I2C0_SDA 4 11 2 3 5 5 A2 I/O I2C0 serial data
Power VSS 7 7 5 6 3 3 D2 P Ground supply
VDD 6 9 4 5 4 4 C2 P Power supply
QFN Pad - - Pad - - Pad - P QFN package exposed thermal pad. TI recommends connection to VSS.
SPI SPI0_CS0 8 8 6 7 - - - I/O SPI0 chip-select 0
SPI0_CS1 4, 13 11, 13 2, 11 3, 9 5 5 A2 I/O SPI0 chip-select 1
SPI0_CS2 19 19 17 15 8 8 A1 I/O SPI0 chip-select 2
SPI0_CS3 2, 18 2, 18 16, 20 14 1 1 B1 I/O SPI0 chip-select 3
SPI0_SCK 10, 11, 13, 15 6, 10, 13, 15 8, 9, 11, 13 8, 9, 11 6 6 D1 I/O SPI0 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI0_POCI 1, 2, 9, 12, 15, 17 1, 2, 5, 15, 17 7, 10, 13, 15, 19, 20 1, 11, 13 1, 6 1, 6 D1, B1 I/O SPI0 controller in/peripheral out
SPI0_PICO 14, 16, 20 14, 16, 20 12, 14, 18 10, 12, 16 7 7 C1 I/O SPI0 controller out/peripheral in
System NRST 5 4 3 4 2 2 B2 I Reset input active low
Timer TIMA_FAL0 1, 10, 11 1, 6, 10 8, 9, 19 1, 8 - - - I/O Advanced control timer fault 0 handling input
TIMA_FAL1 4, 16 11, 16 2, 14 3, 12 5, 7 5, 7 A2, C1 I/O Advanced control timer fault 1 handling input
TIMA_FAL2 2, 20 2, 20 18, 20 16 1 1 B1 I/O Advanced control timer fault 2 handling input
TIMA0_C0 2, 3, 8, 9, 13, 16 2, 3, 5, 8, 13, 16 1, 6, 7, 11, 14, 20 2, 7, 9, 12 1, 7 1, 7 B1, C1 I/O

Advanced control timer 0 CCR0 capture input/compare output
TIMA0_C0N 2, 9, 13 2, 5, 13 7, 11, 20 9 1 1 B1 I/O Advanced control timer 0 CCR0 capture input/compare output (inverting)
TIMA0_C1 5, 9, 10, 12, 14, 17 5, 10, 12, 14, 17 3, 7, 8, 10, 12, 15 4, 8, 10, 13 2 2 B2 I/O

Advanced control timer 0 CCR1 capture input/compare output
TIMA0_C1N 9, 12, 14 5, 14 7, 10, 12 10 - - - I/O Advanced control timer 0 CCR1 capture input/compare output (inverting)
TIMA0_C2 13, 15, 16 13, 15, 16 11, 13, 14 9, 11, 12 6, 7 6, 7 C1, D1 I/O

Advanced control timer 0 CCR2 capture input/compare output
TIMA0_C2N 16 16 14 12 7 7 C1 I/O Advanced control timer 0 CCR2 capture input/compare output (inverting)
TIMA0_C3 13, 14, 18, 19 13, 14, 18, 19 11, 12, 16, 17 9, 10, 14, 15 8 8 A1 I/O

Advanced control timer 0 CCR3 capture input/compare output
TIMA0_C3N 14, 19 14, 19 12, 17 10, 15 8 8 A1 I/O Advanced control timer 0 CCR3 capture input/compare output (inverting)
TIMG14_C0 1, 12, 15, 18 1, 15, 18 10, 13, 16, 19 1, 11, 14 6 6 D1 I/O General purpose timer 0 CCR0 capture input/compare output
TIMG14_C1 10, 18, 19, 20 10, 18, 19, 20 8, 16, 17, 18 8, 14, 15, 16 8 8 A1 I/O General purpose timer 0 CCR1 capture input/compare output
TIMG14_C2 10, 19 10, 19 8, 17 8, 15 8 8 A1 I/O General purpose timer 0 CCR2 capture input/compare output
TIMG14_C3 20 20 18 16 - - - I/O General purpose timer 0 CCR3 capture input/ compare output
TIMG8_C0 1, 4 1, 11 2, 19 1, 3 5 5 A2 I/O General purpose timer 8 CCR0 capture input/compare output
TIMG8_C1 2, 5, 8 2, 8, 12 3, 6, 20 4, 7 1, 2 1, 2 B1, B2 I/O General purpose timer 8 CCR1 capture input/compare output
TIMG8_IDX 3, 8 3, 8 1, 6 2, 7 - - - I

General purpose timer 8 quadtrature encoder index pulse input
UART UART0_TX 2, 13, 18, 20 2, 13, 18, 20 11, 16, 18, 20 9, 14, 16 1 1 B1 O UART0 transmit data
UART0_RX 1, 3, 14, 17, 19 1, 3, 14, 17, 19 1, 12, 15, 17, 19 1, 2, 10, 13, 15 8 8 A1 I UART0 receive data
UART0_CTS 15, 18 15, 18 13, 16 11, 14 6 6 D1 I UART0 "clear to send" flow control input
UART0_RTS 16, 17, 19 16, 17, 19 14, 15, 17 12, 13, 15 7, 8 7, 8 A1, C1 O UART0 "request to send" flow control output
Beeper BEEP 1, 4 1, 11 2, 19 1, 3 5 5 A2 O Beep output
FCC FCC_IN 4, 12 11 2, 10 3 5 6 A2 I Frequency clock counter input
(1) '–' = not available
(2) I = input, O = output, I/O = input or output, P = power