SLASF11C February   2023  – October 2023 MSPM0G1106 , MSPM0G1107

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 GPAMP
      1. 7.15.1 Electrical Characteristics
      2. 7.15.2 Switching Characteristics
    16. 7.16 I2C
      1. 7.16.1 I2C Timing Diagram
      2. 7.16.2 I2C Characteristics
      3. 7.16.3 I2C Filter
    17. 7.17 SPI
      1. 7.17.1 SPI
      2. 7.17.2 SPI Timing Diagram
    18. 7.18 UART
    19. 7.19 TIMx
    20. 7.20 Emulation and Debug
      1. 7.20.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 I2C
    19. 8.19 SPI
    20. 8.20 WWDT
    21. 8.21 RTC
    22. 8.22 Timers (TIMx)
    23. 8.23 Device Analog Connections
    24. 8.24 Input/Output Diagrams
    25. 8.25 Serial Wire Debug Interface
    26. 8.26 Bootstrap Loader (BSL)
    27. 8.27 Device Factory Constants
    28. 8.28 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 DMA

The direct memory access (DMA) controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode, without having to awaken to move data to or from a peripheral.

The DMA in these devices support the following key features:

  • 7 independent DMA transfer channels
    • 3 full-feature channel (DMA0, DMA1 and DMA2), supporting repeated transfer modes
    • 4 basic channels (DMA3, DMA4, DMA5 and DMA6) supporting single transfer modes
  • Configurable DMA channel priorities
  • Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer capability
  • Transfer counter block size supports up to 64k transfers of any data type
  • Configurable DMA transfer trigger selection
  • Active channel interruption to service other channels
  • Early interrupt generation for ping-pong buffer architecture
  • Cascading channels upon completion of activity on another channel
  • Stride mode to support data re-organization, such as 3-phase metering applications

Table 8-2 lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control bits in the DMA memory mapped registers.

Table 8-2 DMA Trigger Mapping
Trigger 0:12 Source Trigger 13:24 Source
0 Software 13 SPI1 Publisher 1
1 Generic Subscriber 0 (FSUB_0) 14 SPI1 Publisher 2
2 Generic Subscriber 1 (FSUB_1) 15 UART3 Publisher 1
7 I2C0 Publisher 1 20 UART1 Publisher 2
8 I2C0 Publisher 2 21 UART2 Publisher 1
9 I2C1 Publisher 1 22 UART2 Publisher 2
10 I2C1 Publisher 2 23 ADC0 Publisher 2
11 SPI0 Publisher 1 24 ADC1 Publisher 2
12 SPI0 Publisher 2
For more details, see the DMA chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.