SLASF11C February   2023  – October 2023 MSPM0G1106 , MSPM0G1107

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 GPAMP
      1. 7.15.1 Electrical Characteristics
      2. 7.15.2 Switching Characteristics
    16. 7.16 I2C
      1. 7.16.1 I2C Timing Diagram
      2. 7.16.2 I2C Characteristics
      3. 7.16.3 I2C Filter
    17. 7.17 SPI
      1. 7.17.1 SPI
      2. 7.17.2 SPI Timing Diagram
    18. 7.18 UART
    19. 7.19 TIMx
    20. 7.20 Emulation and Debug
      1. 7.20.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 I2C
    19. 8.19 SPI
    20. 8.20 WWDT
    21. 8.21 RTC
    22. 8.22 Timers (TIMx)
    23. 8.23 Device Analog Connections
    24. 8.24 Input/Output Diagrams
    25. 8.25 Serial Wire Debug Interface
    26. 8.26 Bootstrap Loader (BSL)
    27. 8.27 Device Factory Constants
    28. 8.28 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.7.1 Memory Organization

The following table summarizes the memory map of the devices. For more information about the memory region detail, see Platform Memory Map section in the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.

Table 8-4 Memory Organization
MEMORY REGIONSUBREGIONMSPM0G1105MSPM0G1106MSPM0G1107
Code (Flash)ECC Corrected

32KB-8B(1)

0x0000.0000 to 0x0000.7FF8

64KB-8B(1)

0x0000.0000 to 0x0000.FFF8

128KB-8B(1)

0x0000.0000 to 0x0001.FFF8
ECC Uncorrected0x0040.0000 to 0x0040.7FF80x0040.0000 to 0x0040.FFF80x0040.0000 to 0x0041.FFF8
SRAM (SRAM) Parity checked 0x2010.0000 to 0x2010.3FFF 0x2010.0000 to 0x2010.7FFF 0x2010.0000 to 0x2010.7FFF
Unchecked 0x2020.0000 to 0x2020.3FFF 0x2020.0000 to 0x2020.7FFF 0x2020.0000 to 0x2020.7FFF
Parity code 0x2030.0000 to 0x2030.3FFF 0x2030.0000 to 0x2030.7FFF 0x2030.0000 to 0x2030.7FFF
PeripheralPeripherals0x4000.0000 to 0x40FF.FFFF0x4000.0000 to 0x40FF.FFFF0x4000.0000 to 0x40FF.FFFF
Flash ECC Corrected0x4100.0000 to 0x4100.80000x4100.0000 to 0x4101.00000x4100.0000 to 0x4102.0000
Flash ECC Uncorrected0x4140.0000 to 0x4140.80000x4140.0000 to 0x4141.00000x4140.0000 to 0x4142.0000
Flash ECC code0x4180.0000 to 0x4180.80000x4180.0000 to 0x4181.00000x4180.0000 to 0x4182.0000
Configuration NVM (NONMAIN) ECC Corrected

512 bytes

0x41C0.0000 to 0x41C0.0200

512 bytes

0x41C0.0000 to 0x41C0.0200

512 bytes

0x41C0.0000 to 0x41C0.0200
Configuration NVM(NONMAIN) ECC Uncorrected0x41C1.0000 to 0x41C1.02000x41C1.0000 to 0x41C1.02000x41C1.0000 to 0x41C1.0200
Configuration NVM(NONMAIN) ECC code0x41C2.0000 to 0x41C2.02000x41C2.0000 to 0x41C2.02000x41C2.0000 to 0x41C2.0200
FACTORY Corrected0x41C4.0000 to 0x41C4.00800x41C4.0000 to 0x41C4.00800x41C4.0000 to 0x41C4.0080
FACTORY Uncorrected0x41C5.0000 to 0x41C5.00800x41C5.0000 to 0x41C5.00800x41C5.0000 to 0x41C5.0080
FACTORY ECC code0x41C6.0000 to 0x41C6.00800x41C6.0000 to 0x41C6.00800x41C6.0000 to 0x41C6.0080
Subsystem0x6000.0000 to 0x7FFF.FFFF0x6000.0000 to 0x7FFF.FFFF0x6000.0000 to 0x7FFF.FFFF
System PPB0xE000.0000 to 0xE00F.FFFF0xE000.0000 to 0xE00F.FFFF0xE000.0000 to 0xE00F.FFFF
(1) The first 32KB flash memory (address 0x0000.0000 to 0x0000.8000) has up to 100000 program/erase cycles.