SLVSJU3 March   2026 MUX808-Q1 , MUX809-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics (±15V Dual Supply)
    7. 6.7  Electrical Characteristics (±36V Dual Supply)
    8. 6.8  Electrical Characteristics (±50V Dual Supply)
    9. 6.9  Electrical Characteristics (72V Single Supply)
    10. 6.10 Electrical Characteristics (100V Single Supply)
    11. 6.11 Switching Characteristics
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Break-Before-Make Delay
    5. 7.5  Enable Turn-on and Turn-off Time
    6. 7.6  Transition Time
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Crosstalk
    10. 7.10 Bandwidth
    11. 7.11 THD + Noise
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Flat On – Resistance
      3. 8.3.3 Protection Features
        1. 8.3.3.1 Fail-Safe Logic
        2. 8.3.3.2 ESD Protection
        3. 8.3.3.3 Latch-Up Immunity
      4. 8.3.4 1.8V Logic Compatible Inputs
      5. 8.3.5 Integrated Pull-Down Resistor on Logic Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3.1 Fail-Safe Logic

Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting the device from potential damage. Additionally the fail safe logic feature allows the logic inputs of the mux to be interfaced with high voltages, allowing for simplified interfacing if only high voltage control signals are present. The logic inputs are protected against positive faults of up to +48V in powered-off condition, but do not offer protection against negative overvoltage condition.

Fail-safe logic also allows the devices to interface with a voltage greater than VDD on the control pins during normal operation to add maximum flexibility in system design. For example, with a VDD = 15V, the logic control pins could be connected to +24V for a logic high signal which allows different types of signals, such as analog feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the logic inputs can be interfaced as high as 48V.