SLLSEJ3A June   2015  – July 2015 ONET1130EC

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Function
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 Transmitter AC Electrical Characteristics
    7. 7.7 Receiver AC Electrical Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmitter
        1. 8.3.1.1 Equalizer
        2. 8.3.1.2 CDR
        3. 8.3.1.3 Modulator Driver
        4. 8.3.1.4 Modulation Current Generator
        5. 8.3.1.5 DC Offset Cancellation and Cross Point Control
        6. 8.3.1.6 Transmitter Loopback (Electrical Loopback)
        7. 8.3.1.7 Bias Current Generation and APC Loop
        8. 8.3.1.8 Laser Safety Features and Fault Recovery Procedure
      2. 8.3.2 Receiver
        1. 8.3.2.1 Equalizer
        2. 8.3.2.2 DC Offset Cancellation and Cross Point Control
        3. 8.3.2.3 CDR
        4. 8.3.2.4 Output Driver
        5. 8.3.2.5 Receiver Loopback (Optical Loopback)
        6. 8.3.2.6 Loss of Signal Detection
      3. 8.3.3 Analog Block
        1. 8.3.3.1 Analog Reference and Temperature Sensor
        2. 8.3.3.2 Power-On Reset
        3. 8.3.3.3 Analog to Digital Converter
        4. 8.3.3.4 2-Wire Interface and Control Logic
        5. 8.3.3.5 Bus Idle
        6. 8.3.3.6 Start Data Transfer
        7. 8.3.3.7 Stop Data Transfer
        8. 8.3.3.8 Data Transfer
      4. 8.3.4 Acknowledge
    4. 8.4 Device Functional Modes
      1. 8.4.1 Differential Transmitter Output
      2. 8.4.2 Single-Ended Transmitter Output
    5. 8.5 Programming
    6. 8.6 Register Mapping
      1. 8.6.1 R/W Control Registers
        1. 8.6.1.1 Core Level Register 0 (offset = 0100 0001 [reset = 41h]
        2. 8.6.1.2 Core Level Register 1 (offset = 0000 0000) [reset = 0h]
        3. 8.6.1.3 Core Level Register 2 (offset = 0000 0000 ) [reset = 0h]
        4. 8.6.1.4 Core Level Register 3 (offset = 0000 0000) [reset = 0h]
      2. 8.6.2 RX Registers
        1. 8.6.2.1 RX Register 4 (offset = 0000 0000) [reset = 0h]
        2. 8.6.2.2 RX Register 5 (offset = 0000 0000) [reset = 0h]
        3. 8.6.2.3 RX Register 6 (offset = 0000 0000) [reset = 0h]
        4. 8.6.2.4 RX Register 7 (offset = 0000 0000) [reset = 0h]
        5. 8.6.2.5 RX Register 8 (offset = 0000 0000) [reset = 0h]
        6. 8.6.2.6 RX Register 9 (offset = 0000 0000) [reset = 0h]
      3. 8.6.3 TX Registers
        1. 8.6.3.1  TX Register 10 (offset = 0000 0000) [reset = 0h]
        2. 8.6.3.2  TX Register 11 (offset = 0000 0000) [reset = 0h]
        3. 8.6.3.3  TX Register 12 (offset = 0000 0000) [reset = 0h]
        4. 8.6.3.4  TX Register 13 (offset = 0h) [reset = 0]
        5. 8.6.3.5  TX Register 14 (offset = 0000 0000) [reset = 0h]
        6. 8.6.3.6  TX Register 15 (offset = 0000 0000) [reset = 0h]
        7. 8.6.3.7  TX Register 16 (offset = 0000 0000) [reset = 0h]
        8. 8.6.3.8  TX Register 17 (offset = 0000 0000) [reset = 0h]
        9. 8.6.3.9  TX Register 18 (offset = 0000 0000) [reset = 0h]
        10. 8.6.3.10 TX Register 19 (offset = 0000 0000) [reset = 0h]
      4. 8.6.4 Reserved Registers
        1. 8.6.4.1 Reserved Registers 20-39
      5. 8.6.5 Read Only Registers
        1. 8.6.5.1 Core Level Register 40 (offset = 0000 0000) [reset = 0h]
        2. 8.6.5.2 Core Level Register 41 (offset = 0000 0000) [reset = 0h]
        3. 8.6.5.3 RX Registers 42 (offset = 0000 0000) [reset = 0h]
        4. 8.6.5.4 TX Register 43 (offset = 0000 0000) [reset = 0h]
      6. 8.6.6 Adjustment Registers
        1. 8.6.6.1 Adjustment Registers 44-50
        2. 8.6.6.2 Adjustment Register 51 (offset = 0100 0000) [reset = 40h]
  9. 9 Application Information and Implementations
    1. 9.1 Application Information
    2. 9.2 Typical Application, Transmitter Differential Mode
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
      4. 9.2.4 Typical Application, Transmitter Single-Ended Mode
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Dual CDR with 9.80-11.7 Gbps Reference-Free Operation
  • 2-Wire Digital Interface with Integrated DACs and ADC for Control and Diagnostic Management
  • Output Polarity Select for TX and RX
  • Programmable Jitter Transfer Bandwidth
  • Electrical and Optical Loopback.
  • CDR Bypass Mode for Low Data Rate Operation
  • Integrated Modulator Driver with Output Amplitude up to 2 VPP Single-ended and Bias Current up to 150 mA Source.
  • Automatic Power Control (APC) Loop with Selectable Monitor PD Range
  • Programmable TX Input Equalizer
  • TX Cross-Point Adjust and De-Emphasis
  • Includes Laser Safety Features
  • Integrated Limiting Amplifier with Programmable LOS Threshold
  • Adjustable RX Equalization and Input Threshold
  • Programmable RX Output Voltage and De-emphasis.
  • Power Supply Monitor and Temperature Sensor
  • Single 2.5-V Supply
  • –40°C to 100°C Operation
  • Surface Mount 4 mm x 4 mm 32-Pin QFN Package with 0.4 mm Pitch

2 Applications

  • XFP and SFP+ 10 Gbps SONET OC-192 Optical Transceivers
  • XFP and SFP+ 10 GBASE-ER/ZR Optical Transceivers

3 Description

The ONET1130EC is a 2.5 V integrated modulator driver and limiting amplifier with transmit and receive clock and data recovery (CDR) designed to operate between 9.80 Gbps and 11.7 Gbps without the need for a reference clock. Optical and electrical loopback are included. CDR bypass mode can be used for operation at lower data rates and a two-wire serial interface allows digital control of the features.

The transmit path consists of an adjustable input equalizer for equalization of up to 300 mm
(12 inches) of microstrip or stripline transmission line of FR4 printed circuit boards, a multi-rate CDR and an output modulator driver. Output waveform control, in the form of cross-point adjustment and de-emphasis are available to improve the optical eye mask margin. Bias current for the laser is provided and an integrated automatic power control (APC) loop to compensate for variations in average optical power over voltage, temperature and time is included.

The receive path consists of a limiting amplifier with programmable equalization and threshold adjustment, a multi-rate CDR and output de-emphasis to compensate for frequency dependent loss of connectors, microstrips or striplines connected to the output of the device, The receiver output amplitude and loss of signal assert level can be adjusted.

Device Information

ORDER NUMBER PACKAGE (PIN) BODY SIZE
ONET1130EC VQFN (32) 4.00 mm x 4.00 mm

Simplified Schematic

ONET1130EC Simp_Schem_Apps_Circ_w_PD_Cathode_SLLSEJ3.gif

4 Revision History

Changes from * Revision (June 2015) to A Revision

  • Changed From: Product Preview To Production Go