SLLSEQ6A September   2016  – September 2016 ONET1131EC

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Function
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagram Definitions
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Equalizer
      2. 7.3.2 CDR
      3. 7.3.3 Modulator Driver
      4. 7.3.4 Modulation Current Generator
      5. 7.3.5 DC Offset Cancellation and Cross Point Control
      6. 7.3.6 Bias Current Generation and APC Loop
      7. 7.3.7 Laser Safety Features and Fault Recovery Procedure
      8. 7.3.8 Analog Block
        1. 7.3.8.1 Analog Reference and Temperature Sensor
        2. 7.3.8.2 Power-On Reset
        3. 7.3.8.3 Analog to Digital Converter
          1. 7.3.8.3.1 Temperature
          2. 7.3.8.3.2 Power Supply Voltage
          3. 7.3.8.3.3 Photodiode Current Monitor
          4. 7.3.8.3.4 Bias Current Monitor
        4. 7.3.8.4 2-Wire Interface and Control Logic
        5. 7.3.8.5 Bus Idle
        6. 7.3.8.6 Start Data Transfer
        7. 7.3.8.7 Stop Data Transfer
        8. 7.3.8.8 Data Transfer
      9. 7.3.9 Acknowledge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Differential Transmitter Output
      2. 7.4.2 Single-Ended Transmitter Output
    5. 7.5 Programming
    6. 7.6 Register Mapping
      1. 7.6.1 R/W Control Registers
        1. 7.6.1.1 Core Level Register 0 (offset = 0100 0001 [reset = 41h]
        2. 7.6.1.2 Core Level Register 1 (offset = 0000 0000) [reset = 0h]
        3. 7.6.1.3 Core Level Register 2 (offset = 0000 0000 ) [reset = 0h]
        4. 7.6.1.4 Core Level Register 3 (offset = 0000 0000) [reset = 0h]
      2. 7.6.2 TX Registers
        1. 7.6.2.1  TX Register 10 (offset = 0000 0000) [reset = 0h]
        2. 7.6.2.2  TX Register 11 (offset = 0000 0000) [reset = 0h]
        3. 7.6.2.3  TX Register 12 (offset = 0000 0000) [reset = 0h]
        4. 7.6.2.4  TX Register 13 (offset = 0h) [reset = 0]
        5. 7.6.2.5  TX Register 14 (offset = 0000 0000) [reset = 0h]
        6. 7.6.2.6  TX Register 15 (offset = 0000 0000) [reset = 0h]
        7. 7.6.2.7  TX Register 16 (offset = 0000 0000) [reset = 0h]
        8. 7.6.2.8  TX Register 17 (offset = 0000 0000) [reset = 0h]
        9. 7.6.2.9  TX Register 18 (offset = 0000 0000) [reset = 0h]
        10. 7.6.2.10 TX Register 19 (offset = 0000 0000) [reset = 0h]
      3. 7.6.3 Reserved Registers
        1. 7.6.3.1 Reserved Registers 20-39
      4. 7.6.4 Read Only Registers
        1. 7.6.4.1 Core Level Register 40 (offset = 0000 0000) [reset = 0h]
        2. 7.6.4.2 Core Level Register 41 (offset = 0000 0000) [reset = 0h]
        3. 7.6.4.3 TX Register 43 (offset = 0000 0000) [reset = 0h]
      5. 7.6.5 Adjustment Registers
        1. 7.6.5.1 Adjustment Registers 44-50
        2. 7.6.5.2 Adjustment Register 51 (offset = 0100 0000) [reset = 40h]
        3. 7.6.5.3 Adjustment Registers 52-55
  8. 8 Application Information and Implementations
    1. 8.1 Application Information
    2. 8.2 Typical Application, Transmitter Differential Mode
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
      4. 8.2.4 Typical Application, Transmitter Single-Ended Mode
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application Information and Implementations

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The ONET1131EC is designed to be used in conjunction with a Transmitter Optical Sub-Assembly (TOSA). The ONET1131EC, TOSA, microcontroller and power management circuitry will typically be used in an XFP or SFP+ 10 Gbps optical transceiver. Figure 46 shows the ONET1131EC in differential mode of operation modulating a differentially driven Mach Zehnder (MZ) modulator TOSA and Figure 48 and Figure 49 show the device in single-ended output mode with an Electroabsorptive Modulated Laser (EML) TOSA. Figure 48 has the photodiode cathode available and Figure 49 has the photodiode anode available.

8.2 Typical Application, Transmitter Differential Mode

ONET1131EC Apps_Circuit_Diff_Mode_SLLSEQ6.gif Figure 46. Typical Application Circuit in Differential Mode

8.2.1 Design Requirements

Table 23. Design Parameters

PARAMETER VALUE
Supply voltage 2.5 V
Transmitter input voltage 100 mVpp to 1000 mVpp differential
Transmitter output voltage 1 Vpp to 3.6 Vpp differential

8.2.2 Detailed Design Procedure

In the transmitter differential mode of operation, the output driver is intended to be used with a differentially driven Mach Zehnder (MZ) modulator TOSA. On the input side, the DIN+ and DIN- pins are required to be AC coupled to the signal from the host system and the input voltage should be between 100 mVpp and 1000 mVpp differential. On the output side, the OUT+ pin is AC coupled to the modulator positive input and the OUT– pin is AC coupled to the modulator negative input. A bias-T from VCC to both the OUT+ and OUT– pins is required to supply sufficient headroom voltage for the output driver transistors. It is recommended that the inductance in the bias-T have low DC resistance to limit the DC voltage drop and maximize the voltage supplied to the OUT+ and OUT– pins. If the voltage on these pins drops below approximately 2.1 V then the output rise and fall times can be adversely affected.

8.2.3 Application Curve

ONET1131EC PG2_V2_TX_DIFF_SLLSEJ3.png Figure 47. Differential Mode Transmitter Output Eye Diagram

8.2.4 Typical Application, Transmitter Single-Ended Mode

ONET1131EC Apps_Circuit_PD_An_Avail_SLLSEQ6.gif Figure 48. Typical Application Circuit in Single-Ended Mode with an EML and the PD Monitor Cathode Available
ONET1131EC Apps_Circuit_PD_Cath_Avail_SLLSEQ6.gif Figure 49. Typical Application Circuit in Single-Ended Mode with an EML and the PD Monitor Anode Available

8.2.4.1 Design Requirements

Table 24. Design Parameters

PARAMETER VALUE
Supply voltage 2.5 V
Transmitter input voltage 100 mVpp to 1000 mVpp differential
Transmitter output voltage 0.5 Vpp to 2 Vpp single-ended

8.2.4.2 Detailed Design Procedure

In the transmitter single-ended mode of operation, the output driver is intended to be used with a single-ended driven Electroabsorptive Modulated Laser (EML) TOSA. On the input side, the DIN+ and DIN– pins are required to be AC coupled to the signal from the host system and the input voltage should be between 100 mVpp and 1000 mVpp differential. On the output side, it is recommended that the OUT+ pin is AC coupled to the modulator input and the OUT– pin can be left unterminated or terminated to VCC through a 50-Ω resistor. A bias-T from VCC to the OUT+ pin is required to supply sufficient headroom voltage for the output driver transistors. It is recommended that the inductance in the bias-T have low DC resistance to limit the DC voltage drop and maximize the voltage supplied to the TXOUT+ pin. If the voltage on this pins drops below approximately 2.1V then the output rise and fall times can be adversely affected.

8.2.4.3 Application Curves

ONET1131EC PG2_V2_TX_SE_SLLSEJ3.png Figure 50. Single-Ended Mode Transmitter Output Eye Diagram