SBOS968C june 2022 – july 2023 OPA186 , OPA2186 , OPA4186
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.8 Typical Characteristics
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)
Table 6-1 Typical Characteristic Graphs
| DESCRIPTION | FIGURE |
|---|---|
| Offset Voltage Distribution | Figure 6-1 |
| Offset Voltage Drift (-40°C to +125C°C) | Figure 6-2 |
| Input Bias Current Distribution | Figure 6-3 |
| Input Offset Current Distribution | Figure 6-4 |
| Offset Voltage vs Common-Mode Voltage | Figure 6-5 |
| Offset Voltage vs Supply Voltage | Figure 6-6 |
| Input Bias Current vs Common-Mode Voltage | Figure 6-7 |
| Open-Loop Gain and Phase vs Frequency | Figure 6-8 |
| Closed-Loop Gain vs Frequency | Figure 6-9 |
| Input Bias Current and Offset Current vs Temperature | Figure 6-10 |
| Output Voltage Swing vs Output Current (Sourcing) | Figure 6-11 |
| Output Voltage Swing vs Output Current (Sinking) | Figure 6-12 |
| CMRR and PSRR vs Frequency | Figure 6-13 |
| CMRR vs Temperature | Figure 6-14 |
| PSRR vs Temperature | Figure 6-15 |
| 0.1-Hz to 10-Hz Voltage Noise | Figure 6-16 |
| Input Voltage Noise Spectral Density vs Frequency | Figure 6-17 |
| THD+N vs Frequency | Figure 6-18 |
| THD+N vs Output Amplitude | Figure 6-19 |
| Quiescent Current vs Supply Voltage | Figure 6-20 |
| Quiescent Current vs Temperature | Figure 6-21 |
| Open-Loop Gain vs Temperature (10 kΩ) | Figure 6-22 |
| Open-Loop Gain vs Temperature (2 kΩ) | Figure 6-23 |
| Open-Loop Output Impedance vs Frequency | Figure 6-24 |
| Small-Signal Overshoot vs Capacitive Load (Gain = –1, 10-mV step) | Figure 6-25 |
| Small-Signal Overshoot vs Capacitive Load (Gain = 1, 10-mV step) | Figure 6-26 |
| No Phase Reversal | Figure 6-27 |
| Positive Overload Recovery | Figure 6-28 |
| Negative Overload Recovery | Figure 6-29 |
| Small-Signal Step Response (Gain = 1, 10-mV step) | Figure 6-30 |
| Small-Signal Step Response (Gain = –1, 10-mV step) | Figure 6-31 |
| Large-Signal Step Response (Gain = 1, 10-V step) | Figure 6-32 |
| Large-Signal Step Response (Gain = –1, 10-V step) | Figure 6-33 |
| Phase Margin vs Capacitive Load | Figure 6-34 |
| Settling Time (1-V Step, 0.1% Settling) | Figure 6-35 |
| Short Circuit Current vs Temperature | Figure 6-36 |
| Maximum Output Voltage vs Frequency | Figure 6-37 |
| EMIRR vs Frequency | Figure 6-38 |
| Channel Separation | Figure 6-39 |
Output Current (Sourcing)
| RL = 2 kΩ |
| Gain = –1, 10-mV step |
Capacitive Load
| Gain = –1, 10-mV step |
| Gain = –1, 10-V step |
| 1-V step, 0.1% settling |
Output Current (Sinking)
| Gain = 1, 10-mV step |
Capacitive Load
| Gain = 1, 10-mV step |
| Gain = 1, 10-V step |
